MICROELECTROMECHANICAL SENSOR DEVICE WITH REDUCED STRESS-SENSITIVITY AND CORRESPONDING MANUFACTURING PROCESS
    76.
    发明申请
    MICROELECTROMECHANICAL SENSOR DEVICE WITH REDUCED STRESS-SENSITIVITY AND CORRESPONDING MANUFACTURING PROCESS 有权
    具有降低应力敏感性的微电子传感器装置和相应的制造工艺

    公开(公告)号:US20170073220A1

    公开(公告)日:2017-03-16

    申请号:US15074755

    申请日:2016-03-18

    Abstract: A MEMS device is provided with: a supporting base, having a bottom surface in contact with an external environment; a sensor die, which is of semiconductor material and integrates a micromechanical detection structure; a sensor frame, which is arranged around the sensor die and is mechanically coupled to a top surface of the supporting base; and a cap, which is arranged above the sensor die and is mechanically coupled to a top surface of the sensor frame, a top surface of the cap being in contact with an external environment. The sensor die is mechanically decoupled from the sensor frame.

    Abstract translation: MEMS装置设置有:支撑基座,其具有与外部环境接触的底面; 传感器芯片,其是半导体材料并且集成了微机械检测结构; 传感器框架,其布置在所述传感器模具周围并且机械地联接到所述支撑基座的顶表面; 以及盖,其布置在传感器模具的上方并且机械地联接到传感器框架的顶表面,盖的顶表面与外部环境接触。 传感器模具与传感器框架机械分离。

    METHOD OF FORMING A PROTECTIVE COATING FOR A PACKAGED SEMICONDUCTOR DEVICE
    79.
    发明申请
    METHOD OF FORMING A PROTECTIVE COATING FOR A PACKAGED SEMICONDUCTOR DEVICE 有权
    形成包装半导体器件的保护涂层的方法

    公开(公告)号:US20170057815A1

    公开(公告)日:2017-03-02

    申请号:US14833871

    申请日:2015-08-24

    Abstract: A first semiconductor substrate having at least one integrated semiconductor device is provided. A lift-off layer is formed on a main surface of the first semiconductor substrate. The lift-off layer is patterned so as to form openings in the lift-off layer that are arranged on either side of a first portion of the lift-off layer. The first substrate is connected together with a second substrate by an interconnect structure to form an assembly with the main surface of the first semiconductor substrate being exposed. Exposed surfaces of the assembly are coated with a parylene coating, with a first portion of the parylene coating being supported by the first portion of the lift-off layer. The first portion of the parylene coating is selectively removed using a lift-off technique that removes the first portion of the lift-off layer. The lift-off technique is performed after connecting the first substrate and second substrates together.

    Abstract translation: 提供具有至少一个集成半导体器件的第一半导体衬底。 在第一半导体衬底的主表面上形成剥离层。 剥离层被图案化以在剥离层中形成布置在剥离层的第一部分的任一侧上的开口。 第一衬底通过互连结构与第二衬底连接在一起,以形成暴露第一半导体衬底的主表面的组件。 组件的暴露表面涂覆有聚对二甲苯涂层,聚对二甲苯涂层的第一部分由剥离层的第一部分支撑。 使用去除剥离层的第一部分的剥离技术选择性地除去聚对二甲苯涂层的第一部分。 在将第一基板和第二基板连接在一起之后进行剥离技术。

    MEMS AND CMOS INTEGRATION WITH LOW-TEMPERATURE BONDING
    80.
    发明申请
    MEMS AND CMOS INTEGRATION WITH LOW-TEMPERATURE BONDING 有权
    MEMS和CMOS集成与低温接合

    公开(公告)号:US20170057814A1

    公开(公告)日:2017-03-02

    申请号:US15170154

    申请日:2016-06-01

    Abstract: The present disclosure relates an integrated chip having one or more MEMS devices. In some embodiments, the integrated chip has a carrier substrate with one or more cavities disposed within a first side of the carrier substrate. A dielectric layer is disposed between the first side of the carrier substrate and a first side of a micro-electromechanical system (MEMS) substrate. The dielectric layer has sidewalls that are laterally set back from sidewalls of openings extending through the MEMs substrate to the one or more cavities. A bonding structure, including an intermetallic compound having a plurality of metallic elements, abuts a second side of the MEMS substrate and is electrically connected to a metal interconnect layer within a dielectric structure disposed over a CMOS substrate.

    Abstract translation: 本公开涉及具有一个或多个MEMS器件的集成芯片。 在一些实施例中,集成芯片具有载体衬底,其具有设置在载体衬底的第一侧内的一个或多个空腔。 电介质层设置在载体衬底的第一侧和微机电系统(MEMS)衬底的第一侧之间。 电介质层具有侧壁,该侧壁从延伸穿过MEM衬底的开口的侧壁横向设置到一个或多个空腔。 包括具有多个金属元素的金属间化合物的接合结构邻接在MEMS基板的第二面上,并且电连接到设置在CMOS基板上的电介质结构内的金属互连层。

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