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71.发明授权Methods and structures for thin-film encapsulation and co-integration of same with microelectronic devices and microelectromechanical systems (MEMS) 有权用于薄膜封装和与微电子器件和微机电系统（MEMS）相结合的方法和结构公开(公告)号：US09428377B2
公开(公告)日：2016-08-30
申请号：US14532658
申请日：2014-11-04
Applicant: Silicon Laboratories Inc.
Inventor： Emmanuel P. Quevy , Jeremy R. Hui , Carrie Wing-Zin Low , Mehrnaz Motiee
CPC classification number: B81C1/00246 , B81B3/0021 , B81B7/007 , B81B7/0077 , B81B7/008 , B81B2201/0214 , B81B2201/0235 , B81B2201/0264 , B81B2203/0127 , B81B2203/0315 , B81C1/00158 , B81C1/00269 , B81C1/00285 , B81C1/00333 , B81C1/0038 , B81C2201/0105 , B81C2201/056 , B81C2203/0118 , B81C2203/0136 , B81C2203/0172 , B81C2203/019 , B81C2203/0735 , G01N27/223 , G01N27/227
Abstract: Methods and structures that may be implemented in one example to co-integrate processes for thin-film encapsulation and formation of microelectronic devices and microelectromechanical systems (MEMS) such as sensors and actuators. For example, structures having varying characteristics may be fabricated using the same basic process flow by selecting among different process options or modules for use with the basic process flow in order to create the desired structure/s. Various process flow sequences as well as a variety of device design structures may be advantageously enabled by the various disclosed process flow sequences.
Abstract translation: 可以在一个示例中实现的方法和结构，以共同整合用于薄膜封装和形成微电子器件和微机电系统（MEMS）例如传感器和致动器的过程。 例如，可以使用相同的基本工艺流程来制造具有不同特性的结构，通过选择与基本工艺流程一起使用的不同工艺选项或模块以便创建所需的结构。 可以通过各种公开的处理流程序列有利地实现各种处理流程序列以及各种设备设计结构。
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公开(公告)号：US20160244323A1
公开(公告)日：2016-08-25
申请号：US15144896
申请日：2016-05-03
Applicant: Asia Pacific Microsystems, Inc.
Inventor： Jerwei Hsieh
IPC: B81B7/00
CPC classification number: B81B7/0038 , B81B7/0058 , B81B2201/032 , B81C1/00238 , B81C1/00817 , B81C1/00825 , B81C2201/053 , B81C2201/056 , B81C2203/0785
Abstract: An integrated MEMS device is provided. The integrated MEMS device comprises a circuit chip and a device chip. The circuit chip has a patterned first bonding layer disposed thereon, the bonding layer being composed of a conductive material/materials. The device chip has a first structural layer and a second structural layer, the first structural layer being connected to the second structural layer and the first bonding layer of the circuit chip, and being sandwiched between the second structural layer and the circuit chip. A plurality of hermetic spaces are enclosed by the first structural layer, the second structural layer, the first bonding layer and the circuit chip.
Abstract translation: 提供集成的MEMS器件。 集成MEMS器件包括电路芯片和器件芯片。 电路芯片具有设置在其上的图案化第一接合层，接合层由导电材料/材料构成。 器件芯片具有第一结构层和第二结构层，第一结构层连接到电路芯片的第二结构层和第一结合层，并夹在第二结构层和电路芯片之间。 第一结构层，第二结构层，第一结合层和电路芯片包围多个封闭空间。
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公开(公告)号：US09359193B2
公开(公告)日：2016-06-07
申请号：US14165752
申请日：2014-01-28
Applicant: Asia Pacific Microsystems, Inc.
Inventor： Jerwei Hsieh
IPC: H01L21/4763 , B81C1/00 , B81B7/00
CPC classification number: B81B7/0038 , B81B7/0058 , B81B2201/032 , B81C1/00238 , B81C1/00817 , B81C1/00825 , B81C2201/053 , B81C2201/056 , B81C2203/0785
Abstract: An integrated MEMS device and its manufacturing method are provided. In the manufacturing method, the sacrificial layer is used to integrate the MEMS wafer and the circuit wafer. The advantage of the present invention comprises preventing films on the circuit wafer from being damaged during process. By the manufacturing method, a mechanically and thermally stable structure material, for example: monocrystalline silicon and polysilicon, can be used. The integrated MEMS device manufactured can also possess the merit of planar top-surface topography with high fill factor. The manufacturing method is especially suitable for manufacturing MEMS array device.
Abstract translation: 提供集成的MEMS器件及其制造方法。 在制造方法中，牺牲层用于集成MEMS晶片和电路晶片。 本发明的优点包括防止电路晶片上的膜在加工过程中被损坏。 通过制造方法，可以使用机械和热稳定的结构材料，例如：单晶硅和多晶硅。 制造的集成MEMS器件也可以具有高填充因子的平面顶表面形貌的优点。 该制造方法特别适用于制造MEMS阵列器件。
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74.发明授权Integration of pressure or inertial sensors into integrated circuit fabrication and packaging 有权将压力或惯性传感器集成到集成电路制造和封装中公开(公告)号：US09260294B2
公开(公告)日：2016-02-16
申请号：US14141875
申请日：2013-12-27
Applicant: Kyu Oh Lee , Sasha N. Oster , Feras Eid , Sarah Haney
Inventor： Kyu Oh Lee , Sasha N. Oster , Feras Eid , Sarah Haney
CPC classification number: G05D16/2026 , B81B3/0027 , B81B7/007 , B81B7/008 , B81B2201/025 , B81B2201/0264 , B81B2203/0127 , B81B2207/094 , B81C1/00158 , B81C1/00238 , B81C1/00246 , B81C1/00333 , B81C1/00547 , B81C2201/056 , B81C2203/0172 , B81C2203/0714 , B81C2203/0792
Abstract: The integration of pressure or inertial sensors into an integrated circuit fabrication and packaging flow is described. In one example, a diaphragm is formed by depositing a metal over a first dielectric layer. A second dielectric layer is formed over the diaphragm. A metal mesh layer is formed over the second dielectric. The first dielectric layer is etched under the diaphragm to form a cavity. The cavity is lined with a sealing layer. The cavity is covered to form a chamber adjoining the diaphragm, and the cover is sealed against the cavity.
Abstract translation: 描述了将压力或惯性传感器集成到集成电路制造和封装流程中。 在一个示例中，通过在第一介电层上沉积金属形成隔膜。 在隔膜上形成第二电介质层。 在第二电介质上形成金属网层。 第一介电层在隔膜下蚀刻形成空腔。 空腔内衬密封层。 空腔被覆盖以形成邻近隔膜的室，并且盖被密封抵靠空腔。
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75.发明申请公开(公告)号：US20160025664A1
公开(公告)日：2016-01-28
申请号：US14532723
申请日：2014-11-04
Applicant: Silicon Laboratories Inc.
Inventor： Emmanuel P. Quevy , Louis Nervegna , Jeremy R. Hui
CPC classification number: B81C1/00246 , B81B3/0021 , B81B7/007 , B81B7/0077 , B81B7/008 , B81B2201/0214 , B81B2201/0235 , B81B2201/0264 , B81B2203/0127 , B81B2203/0315 , B81C1/00158 , B81C1/00269 , B81C1/00285 , B81C1/00333 , B81C1/0038 , B81C2201/0105 , B81C2201/056 , B81C2203/0118 , B81C2203/0136 , B81C2203/0172 , B81C2203/019 , B81C2203/0735 , G01N27/223 , G01N27/227
Abstract: Trapped sacrificial structures and thin-film encapsulation methods that may be implemented to manufacture trapped sacrificial structures such as relative humidity sensor structures, and spacer structures that protect adjacent semiconductor structures extending above a semiconductor die substrate from being contacted by a molding tool or other semiconductor processing tool in an area of a die substrate adjacent the spacer structures.
Abstract translation: 捕获的牺牲结构和薄膜封装方法可用于制造捕获的牺牲结构，例如相对湿度传感器结构，以及保护在半导体管芯基板之上延伸的相邻半导体结构不被模具或其它半导体加工件接触的间隔结构 工具在与衬垫结构相邻的管芯衬底的区域中。
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Patent Agency Ranking
76.发明申请公开(公告)号：US20160023888A1
公开(公告)日：2016-01-28
申请号：US14532658
申请日：2014-11-04
Applicant: Silicon Laboratories Inc.
Inventor： Emmanuel P. Quevy , Jeremy R. Hui , Carrie Wing-Zin Low , Mehrnaz Motiee
CPC classification number: B81C1/00246 , B81B3/0021 , B81B7/007 , B81B7/0077 , B81B7/008 , B81B2201/0214 , B81B2201/0235 , B81B2201/0264 , B81B2203/0127 , B81B2203/0315 , B81C1/00158 , B81C1/00269 , B81C1/00285 , B81C1/00333 , B81C1/0038 , B81C2201/0105 , B81C2201/056 , B81C2203/0118 , B81C2203/0136 , B81C2203/0172 , B81C2203/019 , B81C2203/0735 , G01N27/223 , G01N27/227
Abstract: Methods and structures that may be implemented in one example to co-integrate processes for thin-film encapsulation and formation of microelectronic devices and microelectromechanical systems (MEMS) such as sensors and actuators. For example, structures having varying characteristics may be fabricated using the same basic process flow by selecting among different process options or modules for use with the basic process flow in order to create the desired structure/s. Various process flow sequences as well as a variety of device design structures may be advantageously enabled by the various disclosed process flow sequences.
Abstract translation: 可以在一个示例中实现的方法和结构，以共同整合用于薄膜封装和形成微电子器件和微机电系统（MEMS）例如传感器和致动器的过程。 例如，可以使用相同的基本工艺流程来制造具有不同特性的结构，通过选择与基本工艺流程一起使用的不同工艺选项或模块以便创建所需的结构。 可以通过各种公开的处理流程序列有利地实现各种处理流程序列以及各种设备设计结构。
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77.发明授权Method of manufacturing a semiconductor integrated circuit device having a MEMS element 有权制造具有MEMS元件的半导体集成电路器件的方法公开(公告)号：US09199836B2
公开(公告)日：2015-12-01
申请号：US14452756
申请日：2014-08-06
Applicant: Renesas Electronics Corporation
Inventor： Koichi Arai
CPC classification number: B81B3/0072 , B81B3/00 , B81B2201/0264 , B81B2203/0127 , B81C1/00896 , B81C3/00 , B81C2201/056 , G01L9/0042 , G01L19/06 , H01L29/84 , H01L2224/13 , H01L2924/13091 , H01L2924/1461 , H01L2924/00
Abstract: In a method of manufacturing a semiconductor integrated circuit device having an MEMS element over a single semiconductor chip, the movable part of the MEMS element is fixed before the formation of a rewiring. After formation of the rewiring, the wafer is diced. Then, the movable part of the MEMS element is released by etching the wafer.
Abstract translation: 在制造在单个半导体芯片上具有MEMS元件的半导体集成电路器件的方法中，MEMS元件的可移动部件在形成重新布线之前被固定。 在重新布线形成之后，晶片被切割。 然后，通过蚀刻晶片来释放MEMS元件的可移动部分。
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公开(公告)号：US20150274514A1
公开(公告)日：2015-10-01
申请号：US14165752
申请日：2014-01-28
Applicant: Asia Pacific Microsystems, Inc.
Inventor： Jerwei Hsieh
CPC classification number: B81B7/0038 , B81B7/0058 , B81B2201/032 , B81C1/00238 , B81C1/00817 , B81C1/00825 , B81C2201/053 , B81C2201/056 , B81C2203/0785
Abstract: An integrated MEMS device and its manufacturing method are provided. In the manufacturing method, the sacrificial layer is used to integrate the MEMS wafer and the circuit wafer. The advantage of the present invention comprises preventing films on the circuit wafer from being damaged during process. By the manufacturing method, a mechanically and thermally stable structure material, for example: monocrystalline silicon and polysilicon, can be used. The integrated MEMS device manufactured can also possess the merit of planar top-surface topography with high fill factor. The manufacturing method is especially suitable for manufacturing MEMS array device.
Abstract translation: 提供集成的MEMS器件及其制造方法。 在制造方法中，牺牲层用于集成MEMS晶片和电路晶片。 本发明的优点包括防止电路晶片上的膜在加工过程中被损坏。 通过制造方法，可以使用机械和热稳定的结构材料，例如：单晶硅和多晶硅。 制造的集成MEMS器件也可以具有高填充因子的平面顶表面形貌的优点。 该制造方法特别适用于制造MEMS阵列器件。
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公开(公告)号：US20150185247A1
公开(公告)日：2015-07-02
申请号：US14141759
申请日：2013-12-27
Applicant: Feras Eid , Sasha N. OSTER , Kyu Oh LEE , Sarah HANEY
Inventor： Feras Eid , Sasha N. OSTER , Kyu Oh LEE , Sarah HANEY
CPC classification number: G01P1/04 , B81B3/0027 , B81B7/007 , B81B7/008 , B81B2201/025 , B81B2201/0264 , B81B2203/0127 , B81B2207/094 , B81C1/00238 , B81C1/00246 , B81C1/00333 , B81C1/00547 , B81C2201/056 , B81C2203/0172 , B81C2203/0714 , B81C2203/0792 , G01P15/097 , H01L27/22 , Y10T29/49075
Abstract: Magnet placement is described for integrated circuit packages. In one example, a terminal is applied to a magnet. The magnet is then placed on a top layer of a substrate with solder between the terminal and the top layer, and the solder is reflowed to attach the magnet to the substrate.
Abstract translation: 集成电路封装描述了磁铁放置。 在一个示例中，端子被施加到磁体。 然后将磁体放置在衬底的顶层上，焊料在端子和顶层之间，并且焊料被回流以将磁体附着到衬底上。
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80.发明申请METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A MEMS ELEMENT 有权制造具有MEMS元件的半导体集成电路器件的制造方法公开(公告)号：US20130193536A1
公开(公告)日：2013-08-01
申请号：US13750615
申请日：2013-01-25
Applicant: Koichi ARAI
Inventor： Koichi ARAI
CPC classification number: B81B3/0072 , B81B3/00 , B81B2201/0264 , B81B2203/0127 , B81C1/00896 , B81C3/00 , B81C2201/056 , G01L9/0042 , G01L19/06 , H01L29/84 , H01L2224/13 , H01L2924/13091 , H01L2924/1461 , H01L2924/00
Abstract: In a method of manufacturing a semiconductor integrated circuit device having an MEMS element over a single semiconductor chip, the movable part of the MEMS element is fixed before the formation of a rewiring. After formation of the rewiring, the wafer is diced. Then, the movable part of the MEMS element is released by etching the wafer.
Abstract translation: 在制造在单个半导体芯片上具有MEMS元件的半导体集成电路器件的方法中，MEMS元件的可移动部件在形成重新布线之前被固定。 在重新布线形成之后，晶片被切割。 然后，通过蚀刻晶片来释放MEMS元件的可移动部分。
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