公开(公告)号：US20200008302A1

公开(公告)日：2020-01-02

申请号：US16024713

申请日：2018-06-29

Applicant: Rahul JAIN ,  Prithwish CHATTERJEE ,  Kyu-oh LEE

Inventor： Rahul JAIN ,  Prithwish CHATTERJEE ,  Kyu-oh LEE

IPC: H05K1/18 ,  H01L23/13 ,  H01L25/16 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/34 ,  H05K3/46

Abstract: A package substrate is disclosed. The package substrate includes a substrate core, a cavity below the substrate core that extends from a surface of a first resist layer to a bottom surface of the package substrate, and a first terminal and a second terminal in the first resist layer. The package substrate also includes one or more passive components that are coupled inside the cavity to the first terminal and the second terminal.

公开(公告)号：US20200005994A1

公开(公告)日：2020-01-02

申请号：US16020035

申请日：2018-06-27

Applicant: Kyu-Oh LEE ,  Rahul JAIN ,  Sai VADLAMANI ,  Cheng XU ,  Ji Yong PARK ,  Junnan ZHAO ,  Seo Young KIM

Inventor： Kyu-Oh LEE ,  Rahul JAIN ,  Sai VADLAMANI ,  Cheng XU ,  Ji Yong PARK ,  Junnan ZHAO ,  Seo Young KIM

IPC: H01F27/32 ,  H01F27/28 ,  H01L23/498 ,  H01F41/04 ,  H01L21/48

Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

公开(公告)号：US09607947B2

公开(公告)日：2017-03-28

申请号：US15183645

申请日：2016-06-15

Applicant: Omkar G. Karhade ,  Nevin Altunyurt ,  Kyu Oh Lee ,  Krishna Bharath

Inventor： Omkar G. Karhade ,  Nevin Altunyurt ,  Kyu Oh Lee ,  Krishna Bharath

IPC: H01L23/49 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L23/522 ,  H01L23/498 ,  H01L23/13 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/485

CPC classification number: H01L23/5381 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/538 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83385 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/37002 ,  H01L2924/00 ,  H01L2924/01033

Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.

公开(公告)号：US20150183635A1

公开(公告)日：2015-07-02

申请号：US14141875

申请日：2013-12-27

Applicant: Kyu Oh Lee ,  Sasha N. OSTER ,  Feras EID ,  Sarah HANEY

Inventor： Kyu Oh Lee ,  Sasha N. OSTER ,  Feras EID ,  Sarah HANEY

IPC: B81B7/00 ,  B81C1/00

CPC classification number: G05D16/2026 ,  B81B3/0027 ,  B81B7/007 ,  B81B7/008 ,  B81B2201/025 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2207/094 ,  B81C1/00158 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00333 ,  B81C1/00547 ,  B81C2201/056 ,  B81C2203/0172 ,  B81C2203/0714 ,  B81C2203/0792

Abstract: The integration of pressure or inertial sensors into an integrated circuit fabrication and packaging flow is described. In one example, a diaphragm is formed by depositing a metal over a first dielectric layer. A second dielectric layer is formed over the diaphragm. A metal mesh layer is formed over the second dielectric. The first dielectric layer is etched under the diaphragm to form a cavity. The cavity is lined with a sealing layer. The cavity is covered to form a chamber adjoining the diaphragm, and the cover is sealed against the cavity.

Abstract translation: 描述了将压力或惯性传感器集成到集成电路制造和封装流程中。 在一个示例中，通过在第一介电层上沉积金属来形成隔膜。 在隔膜上形成第二电介质层。 在第二电介质上形成金属网层。 第一介电层在隔膜下蚀刻形成空腔。 空腔内衬密封层。 空腔被覆盖以形成邻近隔膜的室，并且盖被密封抵靠空腔。

公开(公告)号：US20150001733A1

公开(公告)日：2015-01-01

申请号：US13930086

申请日：2013-06-28

Applicant: Omkar G. Karhade ,  Nevin Altunyurt ,  Kyu Oh Lee ,  Krishna Bharath

Inventor： Omkar G. Karhade ,  Nevin Altunyurt ,  Kyu Oh Lee ,  Krishna Bharath

IPC: H01L23/538 ,  H01L23/522

CPC classification number: H01L23/5381 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/538 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83385 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/37002 ,  H01L2924/00 ,  H01L2924/01033

Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.

Abstract translation: 描述了用于电子部件的可靠的微带布线布置。 在一个示例中，半导体器件包括具有其上具有集成电路的表面的半导体管芯，其通过多个导电触点耦合到半导体封装衬底的最上层金属化层的接触焊盘。 多个离散金属平面设置在半导体封装基板的最上层的金属化层上，每个金属平面从平面图的角度位于半导体管芯的周边的角部。 从半导体封装基板的最上层的金属化层设置微带布线，从平面图的角度来看，位于半导体管芯的外围。

公开(公告)号：US09260294B2

公开(公告)日：2016-02-16

申请号：US14141875

申请日：2013-12-27

Applicant: Kyu Oh Lee ,  Sasha N. Oster ,  Feras Eid ,  Sarah Haney

Inventor： Kyu Oh Lee ,  Sasha N. Oster ,  Feras Eid ,  Sarah Haney

IPC: B81B7/00 ,  B81C1/00

CPC classification number: G05D16/2026 ,  B81B3/0027 ,  B81B7/007 ,  B81B7/008 ,  B81B2201/025 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2207/094 ,  B81C1/00158 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00333 ,  B81C1/00547 ,  B81C2201/056 ,  B81C2203/0172 ,  B81C2203/0714 ,  B81C2203/0792

Abstract: The integration of pressure or inertial sensors into an integrated circuit fabrication and packaging flow is described. In one example, a diaphragm is formed by depositing a metal over a first dielectric layer. A second dielectric layer is formed over the diaphragm. A metal mesh layer is formed over the second dielectric. The first dielectric layer is etched under the diaphragm to form a cavity. The cavity is lined with a sealing layer. The cavity is covered to form a chamber adjoining the diaphragm, and the cover is sealed against the cavity.

Abstract translation: 描述了将压力或惯性传感器集成到集成电路制造和封装流程中。 在一个示例中，通过在第一介电层上沉积金属形成隔膜。 在隔膜上形成第二电介质层。 在第二电介质上形成金属网层。 第一介电层在隔膜下蚀刻形成空腔。 空腔内衬密封层。 空腔被覆盖以形成邻近隔膜的室，并且盖被密封抵靠空腔。

公开(公告)号：US20150228583A1

公开(公告)日：2015-08-13

申请号：US14692400

申请日：2015-04-21

Applicant: Omkar G. Karhade ,  Nevin Altunyurt ,  Kyu Oh Lee ,  Krishna Bharath

Inventor： Omkar G. Karhade ,  Nevin Altunyurt ,  Kyu Oh Lee ,  Krishna Bharath

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5381 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/538 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83385 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/37002 ,  H01L2924/00 ,  H01L2924/01033

Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.

公开(公告)号：US20150185247A1

公开(公告)日：2015-07-02

申请号：US14141759

申请日：2013-12-27

Applicant: Feras Eid ,  Sasha N. OSTER ,  Kyu Oh LEE ,  Sarah HANEY

Inventor： Feras Eid ,  Sasha N. OSTER ,  Kyu Oh LEE ,  Sarah HANEY

IPC: G01P15/11 ,  G01P1/04

CPC classification number: G01P1/04 ,  B81B3/0027 ,  B81B7/007 ,  B81B7/008 ,  B81B2201/025 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2207/094 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00333 ,  B81C1/00547 ,  B81C2201/056 ,  B81C2203/0172 ,  B81C2203/0714 ,  B81C2203/0792 ,  G01P15/097 ,  H01L27/22 ,  Y10T29/49075

Abstract: Magnet placement is described for integrated circuit packages. In one example, a terminal is applied to a magnet. The magnet is then placed on a top layer of a substrate with solder between the terminal and the top layer, and the solder is reflowed to attach the magnet to the substrate.

Abstract translation: 集成电路封装描述了磁铁放置。 在一个示例中，端子被施加到磁体。 然后将磁体放置在衬底的顶层上，焊料在端子和顶层之间，并且焊料被回流以将磁体附着到衬底上。

公开(公告)号：US20170064821A1

公开(公告)日：2017-03-02

申请号：US14840979

申请日：2015-08-31

Applicant: Kristof Darmawikarta ,  Daniel Sobieski ,  Kyu Oh Lee ,  Sri Ranga Sai Boyapati

Inventor： Kristof Darmawikarta ,  Daniel Sobieski ,  Kyu Oh Lee ,  Sri Ranga Sai Boyapati

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/40 ,  H05K3/18 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/113 ,  H05K3/0041 ,  H05K3/181 ,  H05K3/188 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09218 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/096 ,  H05K2201/09654 ,  H05K2203/0548

Abstract: Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.

Abstract translation: 一些示例形式涉及电子包装。 电子封装包括第一电介质层，其包括形成在第一电介质层的表面上的电迹线和在第一电介质层的表面上的第二电介质层。 第二电介质层包括开口。 电迹线在开口内。 电子封装包括电互连，其填充开口并且在第二电介质层的上表面上方延伸，使得电互连电连接到第一电介质层上的电迹线。

公开(公告)号：US20160300796A1

公开(公告)日：2016-10-13

申请号：US15183645

申请日：2016-06-15

Applicant: Omkar G. Karhade ,  Nevin Altunyurt ,  Kyu Oh Lee ,  Krishna Bharath

Inventor： Omkar G. Karhade ,  Nevin Altunyurt ,  Kyu Oh Lee ,  Krishna Bharath

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/5381 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/538 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83385 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/37002 ,  H01L2924/00 ,  H01L2924/01033

Abstract: Reliable microstrip routing arrangements for electronics components are described. In an example, a semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.