公开(公告)号：US5950292A

公开(公告)日：1999-09-14

申请号：US811305

申请日：1997-03-04

Applicant: Duane B. Dimos ,  Terry J. Garino

Inventor： Duane B. Dimos ,  Terry J. Garino

IPC: H01L21/60 ,  H01L21/68 ,  H05K1/16 ,  H05K3/20 ,  H01G4/06

CPC classification number: H01L24/82 ,  H01L21/6835 ,  H01L24/24 ,  H05K1/162 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2203/016 ,  H05K3/20 ,  Y10T29/435 ,  Y10T29/49812

Abstract: Applique circuits suitable for advanced packaging applications are introduced. These structures are particularly suited for the simple integration of large amounts (many nanoFarads) of capacitance into conventional integrated circuit and multichip packaging technology. In operation, applique circuits are bonded to the integrated circuit or other appropriate structure at the point where the capacitance is required, thereby minimizing the effects of parasitic coupling. An immediate application is to problems of noise reduction and control in modern high-frequency circuitry.

Abstract translation: 引入适用于先进封装应用的Appliqu + E，acu e + EE电路。 这些结构特别适用于将大量（许多nanoFarads）电容简单集成到传统的集成电路和多芯片封装技术中。 在操作中，贴片+ E，acu e + EE电路在需要电容的位置被结合到集成电路或其他适当的结构，从而最小化寄生耦合的影响。 一个立即的应用是现代高频电路中降噪和控制的问题。

公开(公告)号：US5683791A

公开(公告)日：1997-11-04

申请号：US689692

申请日：1996-08-13

Applicant: Michio Horiuchi ,  Yoichi Harayama

Inventor： Michio Horiuchi ,  Yoichi Harayama

IPC: H05K1/03 ,  B32B37/18 ,  H01L21/48 ,  H05K1/09 ,  H05K3/12 ,  H05K3/24 ,  H05K3/26 ,  H05K3/40 ,  H05K3/46 ,  B32B3/00 ,  B32B15/00

CPC classification number: B32B37/18 ,  H01L21/4857 ,  H01L21/486 ,  H05K1/092 ,  H05K3/4061 ,  H05K1/0306 ,  H05K2201/0317 ,  H05K2203/025 ,  H05K2203/1383 ,  H05K3/245 ,  H05K3/4611 ,  H05K3/4629 ,  Y10S428/901 ,  Y10T156/10 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/252

Abstract: Internal wiring made of copper of low-resistance is provided in a ceramic oxide. Green sheets 10 made of oxide powder are provided with plane wiring 18 and/or via wiring 14 in which copper is used as wiring material. The green sheets 10 are laminated and integrated in such a manner that the wiring portions 4 and 18 are covered with the green sheet so as not to be exposed onto a surface. Then the laminated body is fired at a maximum temperature in a range from 1,083.degree. to 1,800.degree. C.

Abstract translation: 在陶瓷氧化物中设置由低电阻铜制成的内部布线。 由氧化物粉末制成的生片10具有平面布线18和/或通过其中使用铜作为布线材料的布线14。 生片10以这样的方式层叠并整合，使得布线部分4和18被生片覆盖，以便不暴露在表面上。 然后将层压体在最高温度为1083℃至1800℃的范围内烧制。

公开(公告)号：US5617298A

公开(公告)日：1997-04-01

申请号：US575423

申请日：1995-12-20

Applicant: John F. Casey ,  Ronald W. Schroeder ,  Lewis R. Dove ,  Philip J. Yearsley

Inventor： John F. Casey ,  Ronald W. Schroeder ,  Lewis R. Dove ,  Philip J. Yearsley

IPC: H05K1/02 ,  H01C17/065 ,  H01C17/242 ,  H01L23/64 ,  H01L27/01 ,  H05K1/09 ,  H05K1/16 ,  H05K3/02 ,  H01C7/00

CPC classification number: H05K1/167 ,  H01C17/065 ,  H01C17/242 ,  H01L23/647 ,  H01L24/48 ,  H01L24/49 ,  H01L27/013 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/0237 ,  H05K1/092 ,  H05K2201/0317 ,  H05K2201/09236 ,  H05K2203/049 ,  H05K2203/171 ,  H05K3/027

Abstract: A collinear terminated transmission line structure and method for producing same is presented. The structure comprises a plurality of conductors electrically connected to a plurality of resistors. A predetermined spacing between each of the plurality of conductors ranges from 2 mils to 7 mils. Greater spacings are easily accomplished with the present method. The method comprises the steps of screen-printing a resistor swath onto a substrate, the swath being adjacent to one end of the plurality of conductors. After the substrate is dipped into a solution, the resistor swath is laser trimmed to form the plurality of resistors. The substrate is then rinsed with warm water to remove the solution. The solution can be a poly-vinyl alcohol and isopropyl alcohol mixture.

Abstract translation: 提出了共线终端传输线结构及其制造方法。 该结构包括电连接到多个电阻器的多个导体。 多个导体中的每一个之间的预定间隔范围为2密耳至7密耳。 使用本方法可以容易地实现更大的间隔。 该方法包括以下步骤：将电阻丝网丝网印刷到基底上，该条带与多个导体的一端相邻。 在将基板浸入溶液中之后，电阻器条被激光修整以形成多个电阻器。 然后用温水冲洗底物以除去溶液。 该溶液可以是聚乙烯醇和异丙醇混合物。

公开(公告)号：US5483101A

公开(公告)日：1996-01-09

申请号：US341202

申请日：1994-12-05

Applicant: Tadanori Shimoto ,  Koji Matsui

Inventor： Tadanori Shimoto ,  Koji Matsui

IPC: H05K1/03 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H05K1/00 ,  H05K3/38 ,  H05K3/46

CPC classification number: H01L23/5385 ,  H01L23/49894 ,  H01L23/50 ,  H05K3/4602 ,  H01L2924/0002 ,  H01L2924/15312 ,  H01L2924/3011 ,  H05K1/0366 ,  H05K2201/0317 ,  H05K2201/09309 ,  H05K2203/061 ,  H05K2203/1581 ,  H05K3/389 ,  H05K3/467 ,  H05K3/4676

Abstract: A semiconductor package applicable to integrated circuits and other semiconductor devices of the kind needing high integration and high speed operation. The package has a printed circuit board implemented by a glass cloth impregnated with epoxy, bismaleimide-triazine (BT) or similar resin, a power source layer provided in the circuit board in a plate structure, a ground layer formed on the surface of the circuit board in a plate structure, and a thin film laminate wiring formed on the ground layer in a plate structure and consisting of copper and benzocyclobutene. The package desirably shields leakage currents and matches a characteristic impedance with accuracy, thereby noticeably reducing noise and enhancing high speed signal transmission.

Abstract translation: 适用于需要高集成度和高​​速运行的集成电路和其他半导体器件的半导体封装。 该封装具有通过浸渍有环氧树脂，双马来酰亚胺 - 三嗪（BT）或类似树脂的玻璃布实现的印刷电路板，设置在板结构中的电路板中的电源层，形成在电路表面上的接地层 板结构，以及形成在板结构中并由铜和苯并环丁烯组成的地层上的薄膜层叠布线。 封装期望屏蔽泄漏电流并且精确匹配特性阻抗，从而显着降低噪声并增强高速信号传输。

公开(公告)号：US5417800A

公开(公告)日：1995-05-23

申请号：US264308

申请日：1994-06-23

Applicant: Shuji Takeshita

Inventor： Shuji Takeshita

IPC: H01L21/48 ,  H01L23/64 ,  H01L23/66 ,  H05K1/00 ,  H05K1/02 ,  H05K1/03 ,  H05K3/00 ,  H05K3/28 ,  H05K3/46 ,  B44C1/22 ,  B29C37/00 ,  C03C15/00

CPC classification number: H01L23/66 ,  H01L21/4846 ,  H01L23/642 ,  H05K1/024 ,  H05K3/002 ,  H05K3/28 ,  H01L2924/0002 ,  H05K1/036 ,  H05K2201/0154 ,  H05K2201/0187 ,  H05K2201/0317 ,  H05K2203/1184 ,  H05K3/4676 ,  Y10T428/24917

Abstract: A process for manufacturing a thin film circuit board includes forming an insulator layer having a relatively high etching rate in a desired thickness on an insulator layer having a relatively low etching rate and a relatively high dielectric constant, arranging a conductor layer on the insulator layer having a relatively high etching rate, selectively removing the insulator having a relatively high etching rate by etching but excluding a portion located beneath the conductor layer, forming an insulator portion that contains the insulator layer having a relatively high etching rate and supports the conductor layer in the undercut state, forming an insulator layer having a relatively low dielectric constant so as to surround the entire conductor layer, and forming an insulator layer having a relatively high dielectric constant on top of the insulator layer having a relatively low dielectric constant so as to surround the entire insulator layer having a relatively low dielectric constant.

Abstract translation: 一种制造薄膜电路板的方法包括在具有相对低的蚀刻速率和相对高的介电常数的绝缘体层上形成具有希望厚度的较高蚀刻速率的绝缘体层，在具有 相对高的蚀刻速率，通过蚀刻选择性地去除具有相对高的蚀刻速率的绝缘体，但不包括位于导体层下方的部分，形成绝缘体部分，其包含具有相对高的蚀刻速率的绝缘体层并且将导体层支撑在 形成具有相对较低介电常数的绝缘体层，以便围绕整个导体层，并且在具有相对低介电常数的绝缘体层的顶部上形成具有较高介电常数的绝缘体层，以便围绕 整个绝缘体层具有相对低的介电常数 。

公开(公告)号：US5415920A

公开(公告)日：1995-05-16

申请号：US168221

申请日：1993-12-17

Applicant: Kazuaki Satoh ,  Kenji Iida

Inventor： Kazuaki Satoh ,  Kenji Iida

IPC: H05K1/09 ,  H01L21/48 ,  H01L23/498 ,  H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K3/38 ,  B32B9/00

CPC classification number: H05K3/388 ,  H01L21/4846 ,  H01L23/49866 ,  H05K3/108 ,  H01L2924/0002 ,  H05K2201/0154 ,  H05K2201/0317 ,  H05K2203/054 ,  H05K2203/0597 ,  H05K3/062 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A conductive pattern layer structure includes an insulating member containing polyimide, a patterned thin film formed on the insulating member, and a patterned conductive layer formed on the thin film. The patterned conductive layer contains copper. Further, the layer structure includes a patterned barrier layer covering an upper surface and side surfaces of the patterned conductive layer to prevent copper from being diffused into another insulating layer formed around the patterned barrier layer.

Abstract translation: 导电图案层结构包括含有聚酰亚胺的绝缘构件，形成在绝缘构件上的图案化薄膜和形成在薄膜上的图案化导电层。 图案化的导电层含有铜。 此外，层结构包括覆盖图案化导电层的上表面和侧表面的图案化阻挡层，以防止铜扩散到形成在图案化阻挡层周围的另一绝缘层中。

公开(公告)号：US5414224A

公开(公告)日：1995-05-09

申请号：US972450

申请日：1993-01-29

Applicant: Vladimir I. Adasko ,  Arnold K. Vardenburg ,  Alexandr L. Emelyanov ,  Lev A. Seliverstov ,  Viktor L. Emelyanov ,  Alexandr D. Slonimsky ,  Nikolai A. Sklyarov ,  Vladimir I. Tikhonov ,  Jury F. Rogozhin ,  Pogos M. Piliposian

Inventor： Vladimir I. Adasko ,  Arnold K. Vardenburg ,  Alexandr L. Emelyanov ,  Lev A. Seliverstov ,  Viktor L. Emelyanov ,  Alexandr D. Slonimsky ,  Nikolai A. Sklyarov ,  Vladimir I. Tikhonov ,  Jury F. Rogozhin ,  Pogos M. Piliposian

IPC: H05K1/05 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K3/403 ,  H05K1/117 ,  H05K3/4076 ,  H05K3/445 ,  H05K3/4644 ,  H05K3/467 ,  H05K1/056 ,  H05K1/113 ,  H05K2201/0209 ,  H05K2201/0317 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/105 ,  H05K2203/1355 ,  H05K3/0023 ,  H05K3/4608

Abstract: A metal base (1), and holes (12) therein, of a printed circuit board are given an insulating coat (2) produced from an epoxy compound in particulate form which is deposited and machined successively at either side. An insulating topology (16) in a photoresist imposed on the insulating coat (2) is metal-plated in vacuum. On removing the metal from the prominent portions of the topology (16) tracks (4) and connecting pads (5) of a layer (3) of conducting pattern are left. An insulating topology (18) consistent with the disposition of connecting pads (11) and connecting posts (10) interconnecting the layers (3, 6) of conducting patterns is formed and metal-plated. On removing the metal from the prominent portions an insulating layer (9) with connecting posts (10) and connecting pads (11) is left. Next, an insulating topology (19) consistent with the topology of the layer (6) of conducting pattern is formed and metal-plated. After machining, tracks (7) with connecting pads (8) of the layer (6) of conducting pattern are left.

Abstract translation: PCT No.PCT / SU91 / 00055 Sec。 371日期：1993年1月29日 102（e）日期1993年1月29日PCT 1991年4月1日PCT PCT。 第WO92 / 17994号公报 日期为1992年10月15日。印刷电路板上的金属基座（1）和孔（12）被赋予由环形化合物制成的颗粒形式的绝缘涂层（2），其以 侧。 在绝缘涂层（2）上施加的光致抗蚀剂中的绝缘拓扑（16）在真空中进行金属镀覆。 在从拓扑（16）的突出部分移除金属时，留下导电图案层（3）的轨道（4）和连接垫（5）。 形成与连接导电图案的层（3,6）互连的连接焊盘（11）和连接柱（10）一致的绝缘拓扑（18）并进行金属镀覆。 在从突出部分移除金属时，留下具有连接柱（10）和连接垫（11）的绝缘层（9）。 接下来，形成与导电图案层（6）的拓扑一致的绝缘拓扑（19）并进行金属镀覆。 在加工之后，留下具有导电图案层（6）的连接焊盘（8）的轨道（7）。

公开(公告)号：US5406446A

公开(公告)日：1995-04-11

申请号：US201628

申请日：1994-02-25

Applicant: Michael G. Peters ,  William T. Chou ,  Wen-chou V. Wang ,  Michael G. Lee ,  Solomon I. Beilin

Inventor： Michael G. Peters ,  William T. Chou ,  Wen-chou V. Wang ,  Michael G. Lee ,  Solomon I. Beilin

IPC: H01L27/04 ,  H01G4/232 ,  H01G4/30 ,  H01G4/33 ,  H01L21/822 ,  H05K1/11 ,  H05K1/16 ,  H01G1/14

CPC classification number: H01G4/232 ,  H01G4/306 ,  H05K1/162 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/1305 ,  H05K1/112 ,  H05K2201/0317 ,  H05K2201/09309 ,  H05K2203/0315 ,  Y10T29/435 ,  Y10T29/49165

Abstract: A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed and a bottom contact metalization layer is applied to the surface of the bottom contact layers. A portion of the metalization layer is removed and an insulating layer is formed on the surface of the bottom contact metalization layer. A ground metalization feedthrough and a power metalization feedthrough are formed at the surface of the insulating layer. A sequence of top contact layers are applied to the surface of the insulating layer and a front side ground terminal and front side power terminal are formed. A back side ground terminal and a back side power terminal are formed at the back side of the base substrate.

Abstract translation: 通过形成穿过非导电基底基板的厚度的多个通孔并用导电材料填充通孔来形成薄膜旁路电容器，以形成接地通孔和电源通孔。 将背面金属化层序列施加到基底基板的背面。 底部接触层序列被施加到基底基板的前侧表面。 形成底部接触电源端子，并且将底部接触金属化层施加到底部接触层的表面。 去除金属化层的一部分，并在底部接触金属化层的表面上形成绝缘层。 在绝缘层的表面形成接地金属化馈通和功率金属化馈通。 顶层接触层序列被施加到绝缘层的表面，形成前侧接地端子和前端电源端子。 背面接地端子和背面电源端子形成在基底基板的背面。

公开(公告)号：US5399239A

公开(公告)日：1995-03-21

申请号：US992620

申请日：1992-12-18

Applicant: Deepak K. Pai ,  Lowell D. Lund

Inventor： Deepak K. Pai ,  Lowell D. Lund

IPC: H01L21/48 ,  H05K1/05 ,  H05K3/44 ,  H05K3/46 ,  H01L21/00

CPC classification number: H05K3/44 ,  H01L21/4857 ,  H05K1/056 ,  H05K2201/0317 ,  H05K2203/0361 ,  H05K2203/1388 ,  H05K3/467

Abstract: The present invention is an integrated heat sink module and a method of fabricating conductive structures on a substrate. The method of the present invention includes cleaning a substrate material to remove any impurities present on the substrate surface. The method further includes placing a protective layer resilient to chemicals used in conductive structure formation, on a first surface. The first surface is opposite a second surface on which conductive structures are formed. The method includes forming conductive structures on the second surface of the substrate. The protective layer is then removed from the first surface of the substrate.

Abstract translation: 本发明是集成散热器模块和在基板上制造导电结构的方法。 本发明的方法包括清洗衬底材料以除去存在于衬底表面上的任何杂质。 该方法还包括在第一表面上放置一个对导电结构形成中使用的化学物质具有弹性的保护层。 第一表面与其上形成导电结构的第二表面相对。 该方法包括在衬底的第二表面上形成导电结构。 然后从衬底的第一表面去除保护层。

公开(公告)号：US5378310A

公开(公告)日：1995-01-03

申请号：US143642

申请日：1993-11-01

Applicant: Kazuaki Satoh ,  Kenji Iida

Inventor： Kazuaki Satoh ,  Kenji Iida

IPC: H05K1/09 ,  H01L21/48 ,  H01L23/498 ,  H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K3/38 ,  B44C1/22 ,  C23F1/00

CPC classification number: H05K3/388 ,  H01L21/4846 ,  H01L23/49866 ,  H05K3/108 ,  H01L2924/0002 ,  H05K2201/0154 ,  H05K2201/0317 ,  H05K2203/054 ,  H05K2203/0597 ,  H05K3/062 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A method of forming a conductive pattern layer structure includes providing an insulating member containing polyimide, forming a patterned thin film on the insulating member, and forming a patterned conductive layer on the thin film. The patterned conductive layer contains copper. Further, a barrier layer can be patterned to cover an upper surface and side surfaces of the patterned conductive layer to prevent copper from being diffused into another insulating layer formed around the patterned barrier layer.

Abstract translation: 形成导电图案层结构的方法包括提供包含聚酰亚胺的绝缘构件，在绝缘构件上形成图案化薄膜，并在薄膜上形成图案化导电层。 图案化的导电层含有铜。 此外，阻挡层可以被图案化以覆盖图案化导电层的上表面和侧表面，以防止铜扩散到围绕图案化阻挡层形成的另一绝缘层中。