公开(公告)号：US20100020513A1

公开(公告)日：2010-01-28

申请号：US12499364

申请日：2009-07-08

Applicant: Graham Lawson ,  Emmanuel Loiselet

Inventor： Graham Lawson ,  Emmanuel Loiselet

IPC: H05K5/00

CPC classification number: H05K1/0222 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/16152 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/09236 ,  H05K2201/09481 ,  H05K2201/09536 ,  H05K2201/09609 ,  H05K2201/09618 ,  H01L2924/00014

Abstract: An hermetically sealed integrated microwave circuit comprising a coplanar waveguide on a printed circuit board (PCB) electrically connected on one major surface to an integrated circuit, and thermally and electrically connected to a ball grid array (BGA) on its opposite major surface, in which the PCB has at least first and second printed layers, a microwave signal path extends from a ball of the BGA through a through-hole in both printed layers to the coplanar wave guide, and plural ground paths extend from balls of the BGA through first through-holes in the first printed layer of the PCB and through second through-holes of the second printed layer of the PCB, the first and second through-holes being non-coincident, to allow for an hermetic seal across the PCB whilst introducing a predetermined impedance in the PCB between the signal and ground paths.

Abstract translation: 一种密封的集成微波电路，包括在一个主表面上电连接到集成电路的印刷电路板（PCB）上的共面波导，并且在其相对的主表面上热电连接到球栅阵列（BGA），其中 PCB至少具有第一和第二印刷层，微波信号路径从BGA的球通过两个印刷层中的通孔延伸到共面波导，并且多个接地路径从BGA的球从第一至第 在PCB的第一印刷层中的孔和通过PCB的第二印刷层的第二通孔，第一和第二通孔不重合，以允许穿过PCB的气密密封，同时引入预定的 信号与接地路径之间的PCB阻抗。

公开(公告)号：US20100019859A1

公开(公告)日：2010-01-28

申请号：US12180815

申请日：2008-07-28

Applicant: Lance Dion Lascari

Inventor： Lance Dion Lascari

IPC: H01P5/02 ,  H01P3/08

CPC classification number: H01P1/047 ,  H05K1/0222 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/09618 ,  H05K2201/09718

Abstract: A microstripline transmission line arrangement carries a signal having a fundamental frequency. The arrangement includes a first microstripline transmission line, a second microstripline transmission line, and a coaxial electrically conductive conduit interconnecting the first transmission line and the second transmission line. The conduit includes a signal conductor and an electrically grounded shield substantially surrounding the signal conductor. The conductor and the shield are positioned relative to each other to thereby comprise a means for lowpass filtering the signal. A cutoff frequency of the lowpass filtering is less than a third harmonic of the fundamental frequency.

Abstract translation: 微带线传输线路布置具有基频的信号。 该装置包括第一微带线传输线，第二微带线传输线和互连第一传输线和第二传输线的同轴导电导管。 导管包括信号导体和基本上围绕信号导体的电接地屏蔽。 导体和屏蔽件相对于彼此定位，从而包括用于对信号进行低通滤波的装置。 低通滤波的截止频率小于基频的三次谐波。

公开(公告)号：US20100011326A1

公开(公告)日：2010-01-14

申请号：US12499733

申请日：2009-07-08

Applicant: Toshisato Sadamatsu

Inventor： Toshisato Sadamatsu

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H05K1/0218 ,  H05K3/0005 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09618

Abstract: To automatically arrange vias on a printed circuit board so as to satisfy a predetermined condition. A printed circuit board design support method for causing a computer to execute a ground conductive area identifying conductive areas which can be used as grounds of a printed circuit board having a plurality of condicutive layers, an extracting an overlapping conductive area in which the conductive areas identified in the ground conductive area identifying are two-dimensionally overlapped with one another, and an automatic arranging interlayer connection members configured to electrically connect at least two layers with one another among the plurality of conductive areas in the overlapping conductive area extracted in the extracting at an interval within a predetermined distance.

Abstract translation: 在印刷电路板上自动布置通孔以满足预定条件。 一种用于使计算机执行地面导电区域的印刷电路板设计支持方法，所述接地导电区域识别可用作具有多个条理层的印刷电路板的接地的导电区域，提取重叠的导电区域，其中识别出导电区域 在所述接地导电区域识别中彼此二维重叠;以及自动配置层间连接构件，被配置为在所述提取中提取的所述重叠导电区域中的多个导电区域中的至少两层之间彼此电连接 间隔在预定距离内。

公开(公告)号：US20090258538A1

公开(公告)日：2009-10-15

申请号：US12315811

申请日：2008-12-04

Applicant: Roya Yaghmai ,  Frank B. Parrish ,  Daniel DeLessert

Inventor： Roya Yaghmai ,  Frank B. Parrish ,  Daniel DeLessert

IPC: H01R9/05

CPC classification number: H05K1/0243 ,  G01R31/2889 ,  H05K3/3405 ,  H05K2201/09618 ,  H05K2201/09809 ,  H05K2201/09845 ,  H05K2201/10356 ,  H05K2201/10446 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: In one implementation, a method is provided for constructing an interface module which includes constructing a board having a signal via through the board, and having at least one ground via extending through the board. The method further includes back drilling the signal via to create a center conductor hole above a remaining portion of the signal via and back drilling a shield opening in the board and at least part way into the at least one ground via such that a height of the center conductor hole is reduced. The method further includes plating the shield opening and the center conductor hole, and back drilling to remove a portion of the plating to electrically isolate the plated shield opening and the plated center conductor hole.

Abstract translation: 在一个实现中，提供了一种用于构建接口模块的方法，该接口模块包括通过板构建具有信号通孔的板，并且通过板延伸至少一个接地。 该方法还包括：背面钻孔信号通道，以在信号通道的剩余部分上方形成中心导体孔，并且在该板的后面钻出屏蔽开口，并且至少部分地进入至少一个地面，使得 中心导体孔减少。 该方法还包括对屏蔽开口和中心导体孔进行电镀，并进行背面钻孔以去除电镀部分以电隔离电镀屏蔽开口和电镀中心导体孔。

公开(公告)号：US20090244859A1

公开(公告)日：2009-10-01

申请号：US12345069

申请日：2008-12-29

Applicant: Kiyomi MURO ,  Sadahiro Tamai

Inventor： Kiyomi MURO ,  Sadahiro Tamai

IPC: H05K1/00

CPC classification number: H05K1/0218 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0393 ,  H05K3/281 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4664 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09618

Abstract: According to one embodiment, a plurality of bumps are formed by repeatedly applying conductive paste to the conductive pattern portion, a plurality of bump-guiding openings are provided in the cover layer to align with the plurality of bumps, a plurality of crushed portions are formed by crushing heads of the plurality of bumps protruding from the cover layer through the bump-guiding openings, and a ground layer is formed on the cover layer. The ground layer is electrically connected to the plurality of crushed portions.

Abstract translation: 根据一个实施例，通过将导电膏重复地施加到导电图案部分而形成多个凸起，在覆盖层中设置多个凸起引导开口以与多个凸起对准，形成多个压碎部 通过从覆盖层突出的多个凸块的头部通过凸块引导孔破碎，并且在覆盖层上形成接地层。 接地层与多个压碎部电连接。

公开(公告)号：US20090242253A1

公开(公告)日：2009-10-01

申请号：US12345307

申请日：2008-12-29

Applicant: Kiyomi MURO ,  Yasuki TORIGOSHI

Inventor： Kiyomi MURO ,  Yasuki TORIGOSHI

IPC: H05K1/00 ,  H05K1/16

CPC classification number: H05K1/0218 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0393 ,  H05K3/281 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4664 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09618

Abstract: According to one embodiment, a plurality of conductive-paste-filling openings are provided in the cover layer to align with the conductive pattern portion, and a plurality of conductive portions are formed by filling conductive paste in the plurality of conductive-paste-filling openings to conductively join the metal layer to the conductive pattern portion.

Abstract translation: 根据一个实施例，在覆盖层中设置多个导电膏填充开口以与导电图案部分对准，并且通过在多个导电膏填充开口中填充导电糊而形成多个导电部分 将金属层导电地接合到导电图案部分。

公开(公告)号：US07565116B2

公开(公告)日：2009-07-21

申请号：US11268653

申请日：2005-11-08

Applicant: Yuichiro Okuyama ,  Hideya Matsubara ,  Shinya Nakai ,  Masashi Iwata

Inventor： Yuichiro Okuyama ,  Hideya Matsubara ,  Shinya Nakai ,  Masashi Iwata

IPC: H04B1/44 ,  H04B1/40 ,  H04B1/04 ,  H04B1/28 ,  H01Q11/12 ,  H04M1/00 ,  H03F1/14 ,  H03F3/04 ,  H03F3/191 ,  H03F3/14 ,  H01L41/00 ,  H03H9/00 ,  H01P5/12 ,  H01P3/08 ,  H01P1/00

CPC classification number: H05K1/0218 ,  H01L2924/19105 ,  H04B1/0057 ,  H04B1/44 ,  H05K1/0237 ,  H05K1/0298 ,  H05K3/403 ,  H05K2201/09618 ,  H05K2201/09972

Abstract: A high frequency module comprises a layered substrate. Inside the layered substrate, a reception diplexer for processing reception signals and a transmission diplexer for processing transmission signals are provided. The reception diplexer and the transmission diplexer are located in two different regions inside the layered substrate. A conductor portion that is connected to the ground and that electromagnetically separates the reception diplexer and the transmission diplexer from each other is provided between the two regions inside the layered substrate. The conductor portion is formed by using a plurality of through holes.

Abstract translation: 高频模块包括层状衬底。 在层叠基板内设置用于处理接收信号的接收双工器和用于处理传输信号的传输双工器。 接收双工器和发送双工器位于分层基板内的两个不同区域。 在层叠基板内的两个区域之间设置连接到地面并将接收双工器和发送双工器彼此电磁分离的导体部分。 导体部分通过使用多个通孔形成。

公开(公告)号：US20090086451A1

公开(公告)日：2009-04-02

申请号：US12010436

申请日：2008-01-24

Applicant: Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

Inventor： Han Kim ,  Je-Gwang Yoo ,  Chang-Sup Ryu

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K1/0218 ,  H05K1/0236 ,  H05K3/4069 ,  H05K2201/09509 ,  H05K2201/09618 ,  H05K2201/09663 ,  H05K2201/09972

Abstract: A printed circuit board having an embedded cavity capacitor is disclosed. According to an embodiment of the present invention, the printed circuit board having the embedded cavity capacitor, the printed circuit board can include two conductive layers to be used as a power layer and a ground layer, respectively; and a first dielectric layer, placed between the two conductive layers, wherein at least one cavity capacitor is arranged in a noise-transferable path between a noise source and a noise prevented destination which are placed on the printed circuit board, the cavity capacitor being formed to allow a second dielectric layer to have a lower stepped region than the first dielectric layer, the second dielectric layer using the two conductive layers as a first electrode and a second electrode, respectively, and placed between the first electrode and the second electrode.

Abstract translation: 公开了一种具有嵌入式腔体电容器的印刷电路板。 根据本发明的实施例，具有嵌入式空腔电容器的印刷电路板，印刷电路板可以分别包括用作功率层和接地层的两个导电层; 以及放置在所述两个导电层之间的第一电介质层，其中至少一个空腔电容器被布置在放置在所述印刷电路板上的噪声源和被噪声阻止的目的地之间的可噪声转移路径中，形成所述空腔电容器 以允许第二电介质层具有比第一电介质层更低的台阶区域，第二电介质层分别使用两个导电层作为第一电极和第二电极，并且放置在第一电极和第二电极之间。

公开(公告)号：US20090056999A1

公开(公告)日：2009-03-05

申请号：US12198273

申请日：2008-08-26

Applicant: KAZUHIRO KASHIWAKURA

Inventor： KAZUHIRO KASHIWAKURA

IPC: H05K1/11

CPC classification number: H05K1/116 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0243 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809 ,  H05K2201/10189

Abstract: A printed wiring board suppresses characteristic impedance mismatch that occurs when the printed wiring board is equipped with a through-type coaxial connector, and includes ground layers stacked in a plurality of layers via insulating layers; a through-hole; a clearance serving as an anti-pad provided in an area between the through-hole and the ground layers; and signal wiring extending from the through-hole to between prescribed ones of the ground layers through the clearance. The prescribed ones of the ground layers have a wiring-impedance adjustment area for adjusting the impedance of the signal wiring, the wiring-impedance adjustment area being arranged so as to overlap a portion of the signal wiring in the clearance.

Abstract translation: 印刷电路板抑制当印刷电路板配备有通式同轴连接器时发生的特性阻抗失配，并且包括经由绝缘层堆叠成多层的接地层; 通孔; 用作设置在通孔和接地层之间的区域中的防焊盘的间隙; 并且通过间隙从通孔延伸到规定的接地层之间的信号线。 规定的接地层具有用于调整信号布线的阻抗的布线阻抗调整区域，布线阻抗调整区域布置成与间隙中的信号布线的一部分重叠。

公开(公告)号：US07465882B2

公开(公告)日：2008-12-16

申请号：US11610082

申请日：2006-12-13

Applicant: Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

Inventor： Wiren D. Becker ,  Zhaoqing Chen ,  George Katopis

IPC: H05K1/03

CPC classification number: H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0219 ,  H05K1/0253 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09681 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines.

Abstract translation: 通过垂直通孔的信号线导体在用于支撑和互连集成电路芯片的绝缘基板中设置有连接相应电源和接地层的相邻过孔中的屏蔽导体。 通过使用以菱形图案布置的电源平面和接地平面导电网格，​​可以使屏蔽导体存在于信号通孔周围的位置。 电力平面和地平面网格具有彼此的左右镜像关系，并被置换以放置菱形的角部，以避免重叠任何网格线。