公开(公告)号：US07804678B2

公开(公告)日：2010-09-28

申请号：US11844280

申请日：2007-08-23

Applicant: Shih-Hsien Wu ,  Shinn-Juh Lai ,  Min-Lin Lee ,  Shur-Fen Liu

Inventor： Shih-Hsien Wu ,  Shinn-Juh Lai ,  Min-Lin Lee ,  Shur-Fen Liu

IPC: H01G4/06

CPC classification number: H01G4/06 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/14 ,  H01G4/20 ,  H01G4/206 ,  H05K1/162 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09672 ,  H05K2201/2036 ,  Y10T29/417

Abstract: A capacitor device with a capacitance is introduced. The capacitor device includes at least one capacitive element. The at least capacitive element comprises a pair of first conductive layers being opposed to each other, at least one first dielectric layer formed on a surface of at least one of the first conductive layers, and a second dielectric layer being sandwiched between the first conductive layers. The first dielectric layer has a first dielectric constant and the second dielectric layer has a second dielectric constant. The capacitance of the capacitor device depends on dielectric parameters of the first dielectric layer and the second dielectric layer. The dielectric parameters comprise the first dielectric constant and thickness of the at least one first dielectric layer and the second dielectric constant and thickness of the second dielectric layer.

公开(公告)号：US20100180437A1

公开(公告)日：2010-07-22

申请号：US12603071

申请日：2009-10-21

Applicant: William E. McKinzie, III

Inventor： William E. McKinzie, III

IPC: H01R43/00

CPC classification number: H01P1/20 ,  H01P1/2005 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0236 ,  H05K1/0239 ,  H05K1/162 ,  H05K1/165 ,  H05K1/181 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09609 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49018 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A hybrid electromagnetic bandgap (EBG) structure for broadband suppression of noise on printed wiring boards includes an array of coplanar patches interconnected into a grid by series inductances, and a corresponding array of shunt LC networks connecting the coplanar patches to a second conductive plane. This combination of series inductances and shunt resonant vias lowers the cutoff frequency for the fundamental stopband. The series inductances and shunt capacitances may be implemented using surface mount component technology, or printed traces. Patches may also be interconnected by coplanar coupled transmission lines. The even and odd mode impedances of the coupled lines may be increased by forming slots in the second conductive plane disposed opposite to the transmission line, lowering the cutoff frequency and increasing the bandwidth of the fundamental stopband. Coplanar EBG structures may be integrated into power distribution networks of printed wiring boards for broadband suppression of electromagnetic noise.

Abstract translation: 用于宽带抑制印刷电路板上的噪声的混合电磁带隙（EBG）结构包括通过串联电感互连到电网中的共面贴片阵列，以及将共面贴片连接到第二导电平面的相应阵列的分流LC网络。 串联电感和并联谐振通孔的组合降低了基波阻带的截止频率。 串联电感和分流电容可以使用表面贴装元件技术或印刷迹线实现。 补片也可以通过共面耦合传输线相互连接。 可以通过在与传输线相对布置的第二导电平面中形成槽，降低截止频率并增加基带阻带的带宽来增加耦合线的偶模和奇模阻抗。 共面EBG结构可以集成到用于宽带抑制电磁噪声的印刷线路板的配电网络中。

公开(公告)号：US20100170708A1

公开(公告)日：2010-07-08

申请号：US12724239

申请日：2010-03-15

Applicant: Seung Gyo Jeong ,  Yong Seok Choi ,  Ki Pyo Hong

Inventor： Seung Gyo Jeong ,  Yong Seok Choi ,  Ki Pyo Hong

IPC: H05K1/18

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L2224/48091 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/186 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4688 ,  H05K2201/09672 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a capacitor-embedded low temperature co-fired ceramic substrate. A capacitor part is manufactured by firing a deposition including at least one high dielectric ceramic sheet to form a capacitor part. A plurality of low temperature co-fired green sheets are provided. Each of the low temperature co-fired green sheet has at least one of a conductive pattern and a conductive via hole thereon. A low temperature co-fired ceramic deposition is formed by depositing the low temperature co-fired green sheets to embed the capacitor part in the low temperature co-fired ceramic deposition. The embedded capacitor part is connected either to the conductive pattern or the conductive via hole of an adjacent green sheet. Then the low temperature co-fired ceramic deposition having the capacitor part embedded therein is fired.

Abstract translation: 一种制造电容器嵌入式低温共烧陶瓷基板的方法。 通过烧结包括至少一个高介电陶瓷片的沉积来形成电容器部分来制造电容器部分。 提供多个低温共烧生片。 每个低温共烧生片具有导电图案和导电通孔中的至少一个。 通过沉积低温共烧生片将电容器部分嵌入低温共烧陶瓷沉积中形成低温共烧陶瓷沉积。 嵌入式电容器部分连接到相邻生片的导电图案或导电通孔。 然后烧结具有嵌入其中的电容器部分的低温共烧陶瓷沉积。

公开(公告)号：US07741876B2

公开(公告)日：2010-06-22

申请号：US12108739

申请日：2008-04-24

Applicant: Hirotsugu Fusayasu ,  Seiji Hamada ,  Shinichi Tanimoto ,  Ryo Matsubara

Inventor： Hirotsugu Fusayasu ,  Seiji Hamada ,  Shinichi Tanimoto ,  Ryo Matsubara

IPC: H03K19/094 ,  H03K19/0175

CPC classification number: H04B3/34 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/3011 ,  H04L25/0272 ,  H05K1/0245 ,  H05K1/0248 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A differential transmission line that has three or more signal lines and with which there is little unwanted radiation noise is provided. The differential transmission line 2 is provided with three signal lines 2a, 2b, and 2c that transmit differential signals from a differential driver IC1 to a differential receiver IC3, and the majority of the signal lines 2a, 2b, and 2c is provided in conductor layers T2 and T3 of a printed circuit board 4. The signal lines 2a, 2b, and 2c are provided with a signal line parallel segment, a signal line route length adjustment segment that is on the differential driver IC1 side and that connects from differential signal output terminals 1Ea, 1Eb, and 1Ec in the differential driver IC1 to the signal line parallel segment, and a signal line route length adjustment segment that is on the differential receiver IC3 side and that connects from the signal line parallel segment to differential signal input terminals in the differential receiver IC3, wherein the signal lines 2a, 2b, and 2c are formed such that their signal line route length adjustment segments on the differential driver IC1 side are equal in length to one another.

Abstract translation: 提供具有三条或更多条信号线并且几乎不存在不需要的辐射噪声的差分传输线。 差分传输线2设置有将差分信号从差分驱动器IC1传输到差分接收器IC3的三条信号线2a，2b和2c，并且大部分信号线2a，2b和2c设置在导体层 信号线2a，2b，2c设置有信号线并行段，信号线路径长度调节段，位于差分驱动器IC1侧，并从差动信号输出端 差分驱动器IC1中的端子1Ea，1Eb和1Ec与信号线并联段，以及信号线路径长度调节段，位于差分接收器IC3侧，并且从信号线并行段连接到差分信号输入端 差分接收器IC3，其中信号线2a，2b和2c形成为使得它们的信号线路径长度调节段在差分驱动器IC1侧 长度相等。

公开(公告)号：US20100142115A1

公开(公告)日：2010-06-10

申请号：US12499762

申请日：2009-07-08

Applicant: Hyun-Cheol Bae ,  Kwang-Seong Choi ,  Ju Yeon Hong ,  Jong Tae Moon ,  Yong il Jun

Inventor： Hyun-Cheol Bae ,  Kwang-Seong Choi ,  Ju Yeon Hong ,  Jong Tae Moon ,  Yong il Jun

IPC: H01G5/00 ,  H01G7/00 ,  B32B38/04

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01G4/38 ,  H01G4/40 ,  H05K1/0206 ,  H05K1/0306 ,  H05K1/162 ,  H05K3/4629 ,  H05K2201/0187 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2203/171 ,  Y10T29/43 ,  Y10T156/1056

Abstract: Provided are a buried capacitor, a method of manufacturing the same, and a method of changing a capacitance thereof. The buried capacitor includes an upper electrode including at least one first hole, a lower electrode including at least one second hole, and a dielectric interposed between the upper electrode and the lower electrode.

Abstract translation: 提供一种埋电容器，其制造方法和改变其电容的方法。 掩埋电容器包括上电极，其包括至少一个第一孔，包括至少一个第二孔的下电极和介于上电极和下电极之间的电介质。

公开(公告)号：US20100141375A1

公开(公告)日：2010-06-10

申请号：US12316090

申请日：2008-12-09

Applicant: Julius M. Liptak

Inventor： Julius M. Liptak

IPC: H01H85/04

CPC classification number: H01H85/38 ,  H01H85/046 ,  H01H85/463 ,  H01H2085/386 ,  H05K1/0293 ,  H05K2201/086 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09672 ,  H05K2201/09727 ,  H05K2201/10181

Abstract: A circuit interruption device for printed wiring boards having a positive expulsion device for removing melted fuse material, plasma and debris from the printed wiring board.

Abstract translation: 一种用于印刷线路板的电路中断装置，具有用于去除熔化的熔丝材料的正性驱除装置，来自印刷电路板的等离子体和碎屑。

公开(公告)号：US07724117B2

公开(公告)日：2010-05-25

申请号：US12013170

申请日：2008-01-11

Applicant: William R. Goyette ,  Frank B. Winter ,  Eric C. Johnston ,  Hardik Patel

Inventor： William R. Goyette ,  Frank B. Winter ,  Eric C. Johnston ,  Hardik Patel

IPC: H01F5/00

CPC classification number: H05K1/165 ,  H01F17/0013 ,  H01F17/0033 ,  H03H7/0115 ,  H03H2001/0085 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/09672 ,  H05K2201/097

Abstract: A multilayer passive circuit topology is disclosed. In one embodiment, a multilayer circuit is provided. The multilayer circuit comprises a multilayer inductor comprising a first set of parallel conductive traces formed on a first layer, a second set of parallel conductive traces formed on a second layer spaced apart from the first layer; and a plurality of vias that connect respective parallel conductive traces from the first and second layer to form inductor windings. The multilayer circuit further comprises a multilayer capacitor connected to an end of the inductor by a coupling via, the capacitor comprising a first conductive plate and a second conductive plate being spaced apart from one another and being formed on different layers.

Abstract translation: 公开了一种多层无源电路拓扑。 在一个实施例中，提供了多层电路。 多层电路包括多层电感器，其包括形成在第一层上的第一组平行导电迹线，形成在与第一层间隔开的第二层上的第二组平行导电迹线; 以及多个通孔，其将来自第一和第二层的相应的平行导电迹线连接以形成电感器绕组。 多层电路还包括通过耦合通孔连接到电感器的端部的多层电容器，该电容器包括彼此间隔开并形成在不同层上的第一导电板和第二导电板。

公开(公告)号：US07626216B2

公开(公告)日：2009-12-01

申请号：US11583212

申请日：2006-10-18

Applicant: William E. McKinzie, III

Inventor： William E. McKinzie, III

IPC: H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

CPC classification number: H01P1/20 ,  H01P1/2005 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0236 ,  H05K1/0239 ,  H05K1/162 ,  H05K1/165 ,  H05K1/181 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09609 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49018 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A hybrid electromagnetic bandgap (EBG) structure for broadband suppression of noise on printed wiring boards includes an array of coplanar patches interconnected into a grid by series inductances, and a corresponding array of shunt LC networks connecting the coplanar patches to a second conductive plane. This combination of series inductances and shunt resonant vias lowers the cutoff frequency for the fundamental stopband. The series inductances and shunt capacitances may be implemented using surface mount component technology, or printed traces. Patches may also be interconnected by coplanar coupled transmission lines. The even and odd mode impedances of the coupled lines may be increased by forming slots in the second conductive plane disposed opposite to the transmission line, lowering the cutoff frequency and increasing the bandwidth of the fundamental stopband. Coplanar EBG structures may be integrated into power distribution networks of printed wiring boards for broadband suppression of electromagnetic noise.

Abstract translation: 用于宽带抑制印刷电路板上的噪声的混合电磁带隙（EBG）结构包括通过串联电感互连到电网中的共面贴片阵列，以及将共面贴片连接到第二导电平面的相应阵列的分流LC网络。 串联电感和并联谐振通孔的组合降低了基波阻带的截止频率。 串联电感和分流电容可以使用表面贴装元件技术或印刷迹线实现。 补片也可以通过共面耦合传输线相互连接。 可以通过在与传输线相对布置的第二导电平面中形成槽，降低截止频率并增加基带阻带的带宽来增加耦合线的偶模和奇模阻抗。 共面EBG结构可以集成到用于宽带抑制电磁噪声的印刷线路板的配电网络中。

公开(公告)号：US20090275236A1

公开(公告)日：2009-11-05

申请号：US12369543

申请日：2009-02-11

Applicant: David Patrick Murray ,  Bernard Harold Hammond, JR.

Inventor： David Patrick Murray ,  Bernard Harold Hammond, JR.

IPC: H01R13/66 ,  H01R43/20

CPC classification number: H01R13/6466 ,  H01R13/6461 ,  H01R13/6464 ,  H01R13/6658 ,  H01R13/6691 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/53209

Abstract: Methods and systems for providing crosstalk compensation in a jack are disclosed. According to one method, the crosstalk compensation is adapted to compensate for undesired crosstalk generated at a capacitive coupling located at a plug inserted within the jack. The method includes positioning a first capacitive coupling a first time delay away from the capacitive coupling of the plug, the first capacitive coupling having a greater magnitude and an opposite polarity as compared to the capacitive coupling of the plug. The method also includes positioning a second capacitive coupling at a second time delay from the first capacitive coupling, the second time delay corresponding to an average time delay that optimizes near end crosstalk. The second capacitive coupling has generally the same overall magnitude but an opposite polarity as compared to the first capacitive coupling, and includes two capacitive elements spaced at different time delays from the first capacitive coupling.

Abstract translation: 公开了一种用于在千斤顶中提供串扰补偿的方法和系统。 根据一种方法，串扰补偿适于补偿位于插入插座内的插头处的电容耦合处产生的不期望的串扰。 该方法包括将第一时间延迟定位成离开插头的电容耦合的第一电容耦合，与插头的电容耦合相比，第一电容耦合具有更大的幅度和相反的极性。 该方法还包括在第一时间延迟从第一电容耦合定位第二电容耦合，第二时间延迟对应于优化近端串扰的平均时间延迟。 第二电容耦合具有与第一电容耦合相比具有相同的总体幅度但具有相反的极性，并且包括以与第一电容耦合不同的时间延迟隔开的两个电容元件。

公开(公告)号：US20090267702A1

公开(公告)日：2009-10-29

申请号：US12265167

申请日：2008-11-05

Applicant: Sung Young Kim ,  Jin Woo Lee

Inventor： Sung Young Kim ,  Jin Woo Lee

IPC: H01P5/00

CPC classification number: H05K1/0219 ,  H05K1/0245 ,  H05K3/4623 ,  H05K2201/09236 ,  H05K2201/09536 ,  H05K2201/09672

Abstract: A printed circuit board (PCB) capable of decreasing wireless wide area network (WWAN) noise generated due to internal signal interference occurring in the PCB is disclosed. The PCB printed circuit board includes a first layer, a second layer, and at least one insulating layer formed between the first and second layers. The PCB board further includes a first signal line group disposed on the first layer while including a plurality of first signal lines each supplying a first signal, isolation patterns disposed on the first layer such that the isolation patterns are arranged between adjacent ones of the first signal lines, respectively, to prevent the adjacent first signal lines from interfering with each other, and a second signal line group disposed on the second layer while including a plurality of second signal lines each supplying a second signal different from the first signal. The second signal line group corresponds to the isolation patterns.

Abstract translation: 公开了能够减少由于PCB内部信号干扰而产生的无线广域网（WWAN）噪声的印刷电路板（PCB）。 PCB印刷电路板包括第一层，第二层和形成在第一层和第二层之间的至少一个绝缘层。 PCB板还包括设置在第一层上的第一信号线组，同时包括多个提供第一信号的第一信号线，设置在第一层上的隔离图案，使得隔离图案布置在相邻的第一信号之间 线路，以防止相邻的第一信号线彼此干扰;以及第二信号线组，其布置在第二层上，同时包括多个第二信号线，每个第二信号线提供与第一信号不同的第二信号。 第二信号线组对应于隔离模式。