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公开(公告)号：US10256827B2
公开(公告)日：2019-04-09
申请号：US15837312
申请日：2017-12-11
Applicant: Maxlinear, Inc.
Inventor： Sheng Ye
Abstract: A phase locked loop may be operable to generate, utilizing a frequency multiplier, a reference clock signal whose frequency is an integer M times a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the reference clock signal. The phase locked loop may perform an operation of the phase locked loop based on the enabling. The phase locked loop may perform a phase comparison function, based on both rising and falling edges of the crystal clock signal. By utilizing a sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of a charge pump in the phase locked loop, disturbance which is associated with duty cycle errors of the crystal clock signal.
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82.发明授权公开(公告)号：US10224946B2
公开(公告)日：2019-03-05
申请号：US15949395
申请日：2018-04-10
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop
Abstract: Systems and methods are provided for managing dynamic element matching (DEM) in digital-to-analog converters (DACs). One or more parameters associated with the DAC and/or a signal being converted via the DAC; and based on the one or more parameters, conditions affecting dynamic element matching in the DAC may be assessed. Based on the assessing of the conditions, one or more adjustments may be determined and dynamically applied to the dynamic element matching in the DAC.
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公开(公告)号：US20190069040A1
公开(公告)日：2019-02-28
申请号：US16170365
申请日：2018-10-25
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling , Timothy Gallagher , Sridhar Ramesh
IPC: H04N21/6587 , H03M3/00 , H03M1/12 , H03H17/04 , H04N21/61 , H04N7/10 , H04J1/00 , H04H20/42 , H04N21/222 , H04H40/27 , H04N21/6373 , H04H20/77
Abstract: A network device may receive a signal from a headend, wherein a bandwidth of the received signal spans from a low frequency to a high frequency and encompasses a plurality of sub-bands. The network device may determine, based on communication with the headend, whether one of more of the sub-bands residing above a threshold frequency are available for carrying downstream data from the headend to the circuitry. The network device may digitize the signal using an ADC operating at a sampling frequency. The sampling frequency may be configured based on a result of the determining. When the sub-band(s) are available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively high frequency. When the sub-band(s) are not available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively low frequency.
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公开(公告)号：US10218459B2
公开(公告)日：2019-02-26
申请号：US15584198
申请日：2017-05-02
Applicant: Maxlinear, Inc.
Inventor： Seung-Chul Hong , Anand Anandakumar , Curtis Ling
Abstract: Systems and methods for adjusting timing in a communication system, such as an OFDM system are described. In one implementation an error signal is generated to adjust the timing of a variable rate interpolator so as to adjust FFT timing. The error signal may be based on detection of significant peaks in an estimate of the impulse response of the channel, with the peak locations being tracked over subsequent symbols and the system timing adjusted in response to changes in the peaks.
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公开(公告)号：US20190058621A1
公开(公告)日：2019-02-21
申请号：US16160250
申请日：2018-10-15
Applicant: MaxLinear, Inc.
Inventor： Sridhar Ramesh
CPC classification number: H04L27/2621 , H03D1/06 , H03D3/002 , H04B1/1027 , H04B15/00 , H04L27/2601
Abstract: Systems and methods are provided for peak to average power ratio (PAPR) reduction in multichannel transmissions. A plurality of frequency-domain symbols may be generated and assigned to a plurality of subcarriers associated with a multichannel transmission. The subcarriers may be assigned to a plurality of channels used for the multichannel transmission, with a number of the channels being different than a number of the subcarriers. A plurality of time-domain signals corresponding to the plurality of channels may be generated, and an adjustment may be applied to at least one time-domain signal, to generate a corresponding adjusted time-domain signal. The adjustment may be configured based on one or more characteristic associated with at least two of the frequency-domain symbols. Handling related information may be communicated form the transmit-side to the receive-side, such as using spare carriers, to enable handling an output corresponding to the plurality of time-domain signals.
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Patent Agency Ranking
公开(公告)号：US10211868B2
公开(公告)日：2019-02-19
申请号：US14918793
申请日：2015-10-21
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling , Sheng Ye
Abstract: A transceiver comprises local oscillator circuitry, phase noise determination circuitry, mixing circuitry, and digital signal processing circuitry. The local oscillator circuitry is operable to generate a local oscillator signal. The phase noise determination circuitry is operable to introduce a frequency-dependent phase shift to the local oscillator signal to generate a phase-shifted version of the local oscillator signal. The mixing circuitry is operable to mix the local oscillator signal and the phase-shifted version of the local oscillator to generate a baseband signal having an amplitude proportional to a phase difference between the local oscillator signal and the phase-shifted version of the local oscillator signal. The digital signal processing circuitry is operable to process the baseband signal to determine a phase error of the local oscillator signal, and perform signal compensation based on the determined phase error.
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87.发明申请公开(公告)号：US20190044524A1
公开(公告)日：2019-02-07
申请号：US16155482
申请日：2018-10-09
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop
Abstract: In a digital-to-analog converter (DAC) that includes one or more conversion circuits, with each conversion circuit configured to handle one or more bits in an input signal to the DAC, one or more types of errors that occur during operation of the DAC may be detected, and one or more adjustments may be determined for correcting the one or more types of errors that occur during operation of the DAC and/or for reducing effects resulting from the one or more types of errors. At least one of the one or more adjustments may applied, with the at least one of the one or more adjustments is applied to only a subset of one or more conversion circuits. The DAC may be adaptive switched among a plurality of modes, and adjustments may be applied only in one or more of the modes but not in all of the modes.
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88.发明授权公开(公告)号：US10193645B2
公开(公告)日：2019-01-29
申请号：US14316194
申请日：2014-06-26
Applicant: MaxLinear, Inc.
Inventor： Glenn Chang , Brian Sprague , Madhukar Reddy
IPC: H04N7/16 , H04N7/20 , H04N7/18 , H04H40/90 , H04N21/45 , H04N21/41 , H04N21/40 , H04N21/637 , H04N21/6332 , H04N21/647 , H04N21/6402 , H04N21/633 , H04N21/6377 , H04N21/64 , H04N21/61 , H04N21/63 , H04N21/6405 , H04N21/426 , H04N21/6408 , H04N21/60 , H04H20/63 , H04N7/10 , H04N7/22 , H04N21/436
Abstract: A satellite reception assembly may comprise a housing configured to support receipt and handling of a plurality of satellite signals. The housing may comprise circuitry incorporating integrated stacking architecture for supporting and/or providing channel and/or band stacking whereby particular channels or bands, from multiple satellite signals that are received via the satellite reception assembly, may be combined onto a single output signal that may be communicated from the satellite reception assembly to a gateway device for concurrent distribution thereby to a plurality of client devices serviced by the gateway device.
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公开(公告)号：US20190028908A1
公开(公告)日：2019-01-24
申请号：US16109530
申请日：2018-08-22
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling
Abstract: A communications network comprises performance determination circuitry and link control circuitry. The performance determination circuitry is operable to determine performance of a microwave backhaul link between a first microwave backhaul transceiver and a second microwave backhaul transceiver. The microwave backhaul link backhauls traffic of a mobile access link. The link control circuitry is operable to, in response to an indication from the performance determination circuitry that the performance of the microwave backhaul link has degraded, adjust one or more signaling parameters used for the mobile access link. The link control circuitry is operable to, in response to the indication that the performance of the microwave backhaul link has degraded, adjust one or more signaling parameters used for the backhaul link in combination with the adjustment of the parameter(s) of the access link.
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公开(公告)号：US20190020513A1
公开(公告)日：2019-01-17
申请号：US16136322
申请日：2018-09-20
Applicant: Maxlinear, Inc.
Inventor： Ioannis Spyropoulos , Anand Anandakumar
CPC classification number: H04L25/03184 , H04B1/16
Abstract: An electronic receiver may generate a differential detection sequence based on a received symbol sequence and based on a m-symbol delayed version of the received symbol sequence, where in is an integer greater than 1. The particular differential detection sequence may be a result of an element-by-element multiplication of the particular received symbol sequence and the conjugate of an in-symbol delayed version of the particular received symbol sequence. The receiver may calculate differential decision metrics based on the differential detection sequence and based on a set of differential symbol sequences generated from the set of possible transmitted symbol sequences. The receiver may generate a decision as to which of a set of possible transmitted symbol sequences resulted in the received symbol sequence, where the decision is based on the differential decision metrics and the set of possible transmitted symbols sequences.
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