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公开(公告)号：US20200006631A1
公开(公告)日：2020-01-02
申请号：US16024411
申请日：2018-06-29
Applicant: Intel Corporation
Inventor： Noriyuki Sato , Tanay Gosavi , Justin Brockman , Sasikanth Manipatruni , Kaan Oguz , Kevin O'Brien , Christopher Wiegand , Angeline Smith , Tofizur Rahman , Ian Young
Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a magnetic tunnel junction (MTJ) device on a portion of the electrode. The electrode has a first SOC layer and a second SOC layer on a portion of the first SOC layer, where at least a portion of the first SOC layer at an interface with the second SOC layer includes oxygen.
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82.发明申请公开(公告)号：US20200006626A1
公开(公告)日：2020-01-02
申请号：US16022094
申请日：2018-06-28
Applicant: Intel Corporation
Inventor： Angeline Smith , Ian Young , Kaan Oguz , Sasikanth Manipatruni , Christopher Wiegand , Kevin O'Brien , Tofizur Rahman , Noriyuki Sato , Benjamin Buford , Tanay Gosavi
Abstract: An insertion layer for perpendicular spin orbit torque (SOT) memory devices between the SOT electrode and the free magnetic layer, memory devices and computing platforms employing such insertion layers, and methods for forming them are discussed. The insertion layer is predominantly tungsten and improves thermal stability and perpendicular magnetic anisotropy in the free magnetic layer.
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公开(公告)号：US20200006424A1
公开(公告)日：2020-01-02
申请号：US16022564
申请日：2018-06-28
Applicant: Intel Corporation
Inventor： Noriyuki Sato , Angeline Smith , Tanay Gosavi , Sasikanth Manipatruni , Kaan Oguz , Kevin O'Brien , Tofizur Rahman , Gary Allen , Atm G. Sarwar , Ian Young , Hui Jae Yoo , Christopher Weigand , Benjamin Buford
Abstract: A spin orbit torque (SOT) memory device includes a magnetic tunnel junction (MTJ) device with one end coupled with a first electrode and an opposite end coupled with a second electrode including a spin orbit torque material. In an embodiment, a second electrode is coupled with the free magnet and coupled between a pair of interconnect line segments. The second electrode and the pair of interconnect line segments include a spin orbit torque material. The second electrode has a conductive path cross-section that is smaller than a cross section of the conductive path in at least one of the interconnect line segments.
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84.发明申请公开(公告)号：US20190386205A1
公开(公告)日：2019-12-19
申请号：US16012672
申请日：2018-06-19
Applicant: Intel Corporation
Inventor： Tanay Gosavi , Sasikanth Manipatruni , Kaan Oguz , Noriyuki Sato , Kevin O'Brien , Benjamin Buford , Christopher Wiegand , Angeline Smith , Tofizur Rahman , Ian Young
Abstract: An apparatus is provided which comprises: a magnetic junction including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device; a second structure comprising one of a dielectric or metal; a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure comprising an antiferromagnetic (AFM) material, the fourth structure adjacent to the third structure; a fifth structure comprising a magnet with PMA, the fifth structure adjacent to the fourth structure; and an interconnect adjacent to the first structure, the interconnect comprising spin orbit material.
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85.发明申请公开(公告)号：US20190386203A1
公开(公告)日：2019-12-19
申请号：US16012673
申请日：2018-06-19
Applicant: Intel Corporation
Inventor： Tanay Gosavi , Chia-Ching Lin , Sasikanth Manipatruni , Ian Young
Abstract: An apparatus is provided which comprises: a bit-line; a first word-line; a second word-line; and a source-line; a magnetic junction comprising a free magnet; an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the free magnet of the magnetic junction; and a first device (e.g., a selector device) coupled at one end of the interconnect and to the second word-line; and a second device coupled to the magnetic junction, the first word-line and the source-line.
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Patent Agency Ranking
公开(公告)号：US20190325932A1
公开(公告)日：2019-10-24
申请号：US16464260
申请日：2016-12-23
Applicant: Intel Corporation
Inventor： Sasikanth Manipatruni , Dmitri E. Nikonov , Ian A. Young
Abstract: An apparatus is provided which comprises: a first paramagnet; a stack of layers, a portion of which is adjacent to the first paramagnet, wherein the stack of layers is to provide an inverse Rashba-Edelstein effect; a second paramagnet; a magnetoelectric layer adjacent to the second paramagnet; and a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.
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公开(公告)号：US10331582B2
公开(公告)日：2019-06-25
申请号：US15430765
申请日：2017-02-13
Applicant: INTEL CORPORATION
Inventor： Ishwar S. Bhati , Huichu Liu , Jayesh Gaur , Kunal Korgaonkar , Sasikanth Manipatruni , Sreenivas Subramoney , Tanay Karnik , Hong Wang , Ian A. Young
IPC: G06F13/16 , G06F12/0811
Abstract: A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.
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公开(公告)号：US20190036018A1
公开(公告)日：2019-01-31
申请号：US16081001
申请日：2016-03-29
Applicant: INTEL CORPORATION
Inventor： Sasikanth Manipatruni , Ian A. Young , Dmitri E. Nikonov , Ravi Pillarisetty , Uygar E. Avci
Abstract: Described is an apparatus which comprises: a heat spreading layer; a first transition metal layer adjacent to the heat spreading layer; and a magnetic recording layer adjacent to the first transition metal layer. Described is an apparatus which comprises: a first electrode; a magnetic junction having a free magnet; and one or more layers of Jahn-Teller material adjacent to the first electrode and the free magnet of the magnetic junction.
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公开(公告)号：US10074357B2
公开(公告)日：2018-09-11
申请号：US14877602
申请日：2015-10-07
Applicant: Intel Corporation
Inventor： Sasikanth Manipatruni , Kelin J. Kuhn , Debendra Mallik , John C. Johnson
CPC classification number: G10K11/346 , A41D2400/00 , H04R1/403 , H04R1/406 , H04R2201/023 , H04R2201/401 , H04R2499/11 , H04R2499/15
Abstract: A system includes a processor and a phased array, coupled to the processor, having an arrayed waveguide for acoustic waves to enable directional sound communication.
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公开(公告)号：US09947805B2
公开(公告)日：2018-04-17
申请号：US15151381
申请日：2016-05-10
Applicant: Intel Corporation
Inventor： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
IPC: H01H51/22 , H01L29/84 , H01H59/00 , B82Y10/00 , H01H1/00 , H01L29/04 , H01L29/06 , H01L29/161 , H01H9/02
CPC classification number: H01L29/84 , B82Y10/00 , H01H1/0094 , H01H9/0271 , H01H59/0009 , H01L29/045 , H01L29/0673 , H01L29/161
Abstract: Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
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