公开(公告)号：US09823849B2

公开(公告)日：2017-11-21

申请号：US14752812

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Mark A. Schmisseur ,  Mohan J. Kumar ,  Balint Fleischer ,  Debendra Das Sharma ,  Raj K. Ramanujan

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0685

Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.

公开(公告)号：US20170270062A1

公开(公告)日：2017-09-21

申请号：US15198605

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma

IPC: G06F13/16 ,  G06F11/10 ,  G06F13/42

Abstract: Data is accessed from a particular register first device that is connected to a second device via a link that includes at least one retimer device. The particular register corresponds to requests to be sent in in-band transactions with the retimer, and the data corresponds to a particular transaction with the retimer. At least one ordered set is generated at the first device to comprise a subset of bits encoded with the data, where the ordered set with the encoded subset of bits is to be sent on the link and the subset of bits are to be processed by the retimer in the particular transaction.

公开(公告)号：US20170235701A1

公开(公告)日：2017-08-17

申请号：US15503097

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Akshay Pethe ,  Mahesh Wagh ,  David Harriman ,  Su Wei Lim ,  Debendra Das Sharma ,  Daniel Froelich ,  Venkatraman Iyer ,  James Jaussi ,  Zuoguo Wu

IPC: G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4286 ,  G06F13/385 ,  G06F13/4027 ,  G06F2213/0042 ,  G06F2213/4002

Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.

公开(公告)号：US09720838B2

公开(公告)日：2017-08-01

申请号：US14670578

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC: G06F12/00 ,  G06F12/084 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F12/084 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0673 ,  G06F12/0806 ,  G06F12/0808 ,  G06F13/1673 ,  G06F13/4282 ,  G06F2212/1016 ,  G06F2212/60 ,  G06F2212/62

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.

公开(公告)号：US20170052860A1

公开(公告)日：2017-02-23

申请号：US15176185

申请日：2016-06-08

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Mohan J. Kumar ,  Balint Fleischer

IPC: G06F11/20

CPC classification number: G06F11/2094 ,  G06F11/108 ,  G06F11/1088 ,  G06F11/2043 ,  G06F11/2087 ,  G06F11/2092 ,  G06F11/2097 ,  G06F12/08 ,  G06F12/0833 ,  G06F12/0837 ,  G06F15/16 ,  G06F2201/805 ,  G06F2201/82

Abstract: An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.

Abstract translation: 本文描述了跨多个集群的相干共享存储器的装置。 该装置包括织物存储器控制器和一个或多个节点。 织物存储器控制器管理对每个节点的共享存储器区域的访问，使得即使响应于节点的故障，每个共享存储器区域也可以使用加载存储器语义来访问。 该设备还包括全局存储器，其中每个共享存储器区域被结构存储器控制器映射到全局存储器。

公开(公告)号：US20160335148A1

公开(公告)日：2016-11-17

申请号：US15042463

申请日：2016-02-12

Applicant: Intel Corporation

Inventor： Prahladachar Jayaprakash Bharadwaj ,  Alexander Brown ,  Debendra Das Sharma ,  Junaid Thaliyil

IPC: G06F11/07

CPC classification number: G06F11/0745 ,  G06F11/0736 ,  G06F11/0793 ,  G06F11/1415 ,  G06F11/1443

Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

Abstract translation: 在串行数据链路的端口处识别分组，并且确定分组与错误相关联。 基于确定该分组与该错误相关联来进入错误恢复模式。 进入错误恢复模式可能导致串行数据链路被强制关闭。 在一个方面，强制数据链路断开导致所有后续入站分组被丢弃，并且所有待处理的出站请求和完成将在错误恢复模式期间中止。

公开(公告)号：US20160283303A1

公开(公告)日：2016-09-29

申请号：US14671881

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F11/079 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/0793

Abstract: A shared memory controller receives a memory access request from a computing node, the request corresponding to a particular line of pooled memory. An error corresponding to the request is identified and the request is forwarded to a second shared memory controller in response to the error. A response is received to the request from the second shared memory controller. The response can be forwarded to the computing node by the shared memory controller.

Abstract translation: 共享存储器控制器从计算节点接收存储器访问请求，该请求对应于合并存储器的特定行。 识别与该请求相对应的错误，并且响应于该错误将该请求转发到第二共享存储器控制器。 接收到来自第二共享存储器控制器的请求的响应。 响应可以由共享存储器控制器转发到计算节点。

公开(公告)号：US09442855B2

公开(公告)日：2016-09-13

申请号：US14583601

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC: G06F3/00 ,  G06F13/14 ,  G06F12/08 ,  G06F1/32 ,  H04L12/66 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

公开(公告)号：US20160179710A1

公开(公告)日：2016-06-23

申请号：US14580918

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Daniel S. Froelich ,  Venkatraman Iyer ,  Michelle C. Jen ,  Rahul R. Shah ,  Eric M. Lee

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/385 ,  G06F13/4282

Abstract: An apparatus that includes a physical interface for a serial interconnect is provided. The physical interface includes a buffer that is selectable to function as a drift buffer or an elastic buffer by a voltage level on a buffer control line. The physical interface also includes encoding logic that can be enabled or disabled by a voltage level on a logic control line. Further, the physical interface also includes and an ordered set generator that can be enabled or disabled by a voltage level on a communications control line.

Abstract translation: 提供了一种包括用于串行互连的物理接口的装置。 物理接口包括缓冲器，其可选择用作缓冲器控制线上的电压电平的漂移缓冲器或弹性缓冲器。 物理接口还包括可由逻辑控制线上的电压电平启用或禁用的编码逻辑。 此外，物理接口还包括可以通过通信控制线上的电压电平启用或禁用的有序集发生器。

公开(公告)号：US09208121B2

公开(公告)日：2015-12-08

申请号：US14538937

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Venkatraman Iyer ,  Darren S. Jue ,  Robert G. Blankenship ,  Fulvio Spagna ,  Debendra Das Sharma ,  Jeffrey C. Swanson

IPC: G06F13/42 ,  G06N99/00

CPC classification number: G06F13/4291 ,  G06F1/24 ,  G06F1/3287 ,  G06F13/1678 ,  G06F13/42 ,  G06F13/4282 ,  G06N99/005

Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.

Abstract translation: 周期性控制窗口嵌入在要通过串行数据链路发送的链路层数据流中，其中控制窗口被配置为提供物理层信息，包括用于启动数据链路上的状态转换的信息。 可以在数据链路的链路发送状态期间发送链路层数据，并且控制窗口可以中断发送猝发。 在一个方面，信息包括指示改变链路上的活动车道数目的尝试的链路宽度转换数据。