公开(公告)号：US10665707B2

公开(公告)日：2020-05-26

申请号：US15771752

申请日：2015-12-02

Applicant: INTEL CORPORATION

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic

IPC: H01L29/778 ,  H01L29/267 ,  H01L29/20 ,  H01L29/24 ,  H01L21/8258 ,  H01L27/092

Abstract: Techniques are disclosed for co-integrating transition metal dichalcogenide (TMDC)-based p-channel transistor devices and III-N semiconductor-based n-channel transistor devices. In accordance with some embodiments, a p-channel transistor device configured as described herein may include a layer of TMDC material such as, for example, tungsten diselenide, tungsten disulfide, molybdenum diselenide, or molybdenum disulfide, and an n-channel transistor device configured as described herein may include a layer of III-V material such as, for example, gallium nitride, aluminum nitride, aluminum gallium nitride, and indium aluminum nitride. Transistor structures provided as described herein may be utilized, for instance, in power delivery applications where III-N semiconductor-based n-channel power transistor devices can benefit from being integrated with low-leakage, high-performance p-channel devices providing logic and control circuitry. In some cases, a TMDC-based transistor provided as described herein may exhibit p-channel mobility in excess of bulk Si and thus may exhibit faster performance than traditional Si-based p-channel transistors.

公开(公告)号：US10658487B2

公开(公告)日：2020-05-19

申请号：US15772783

申请日：2015-12-09

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Han Wui Then ,  John J. Plombon ,  Michael L. McSwiney

IPC: H01L29/49 ,  H01L21/285 ,  H01L23/532 ,  C23C16/30 ,  H01L21/768 ,  H01L21/28 ,  H01L27/088

Abstract: Embodiments of the present disclosure describe semiconductor devices with ruthenium phosphorus thin films and further describe the processes to deposit the thin films. The thin films may be deposited in a gate stack of a transistor device or in an interconnect structure. The processes to deposit the films may include chemical vapor deposition and may include ruthenium precursors. The precursors may contain phosphorus. A co-reactant may be used during deposition. A co-reactant may include a phosphorus based compound. A gate material may be deposited on the film in a gate stack. The ruthenium phosphorus film may be a metal diffusion barrier and an adhesion layer, and the film may be a work function metal for some embodiments. Other embodiments may be described and/or claimed.

公开(公告)号：US20200152855A1

公开(公告)日：2020-05-14

申请号：US16631681

申请日：2017-09-20

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Nicholas James Harold McKubre ,  Han Wui Then

IPC: H01L41/09 ,  H01F27/30 ,  H01L49/02 ,  H01F27/24

Abstract: Disclosed herein are inductor/core assemblies for integrated circuits (ICs), as well as related structures, methods, and devices. In some embodiments, an IC structure may include an inductor and a magnetic core in an interior of the inductor. The magnetic core may be movable perpendicular to a plane of the inductor.

公开(公告)号：US10535777B2

公开(公告)日：2020-01-14

申请号：US15940424

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/20 ,  H01L29/04 ,  H01L29/423 ,  H01L21/306 ,  H01L21/02

Abstract: Nanoribbon Field Effect Transistors (FETs) offer significant performance increases and energy consumption decreases relative to traditional metal oxide semiconductor (MOS) transistors. Various embodiments are directed to nanoribbon FETs having III-N channel materials and methods of forming the same. An integrated circuit (IC) structure can include a first layer on a substrate. The first layer can include a group III semiconductor material and nitrogen. The IC structure can include recessed source and drain regions formed on the first layer using planar epitaxy. The IC structure can include a second layer between the recessed source and drain. A gate wraps around at least part of the second layer.

公开(公告)号：US10475888B2

公开(公告)日：2019-11-12

申请号：US15492785

申请日：2017-04-20

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Robert S. Chau

IPC: H01L29/20 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02

Abstract: An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.

公开(公告)号：US20190305135A1

公开(公告)日：2019-10-03

申请号：US15940424

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/20 ,  H01L29/04 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306

Abstract: Nanoribbon Field Effect Transistors (FETs) offer significant performance increases and energy consumption decreases relative to traditional metal oxide semiconductor (MOS) transistors. Various embodiments are directed to nanoribbon FETs having III-N channel materials and methods of forming the same. An integrated circuit (IC) structure can include a first layer on a substrate. The first layer can include a group III semiconductor material and nitrogen. The IC structure can include recessed source and drain regions formed on the first layer using planar epitaxy. The IC structure can include a second layer between the recessed source and drain. A gate wraps around at least part of the second layer.

公开(公告)号：US20190287858A1

公开(公告)日：2019-09-19

申请号：US16433277

申请日：2019-06-06

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Sanaz Gardner ,  Seung Hoon Sung

IPC: H01L21/8258 ,  H01L21/02 ,  H01L21/8252 ,  H01L27/085 ,  H01L27/06 ,  H01L29/08 ,  H01L27/092 ,  H01L29/778 ,  H01L29/66

Abstract: Techniques are disclosed for fabricating co-planar p-channel and n-channel gallium nitride (GaN)-based transistors on silicon (Si). In accordance with some embodiments, a Si substrate may be patterned with recessed trenches located under corresponding openings formed in a dielectric layer over the substrate. Within each recessed trench, a stack including a buffer layer, a GaN or indium gallium nitride (InGaN) layer, and a polarization layer may be selectively formed, in accordance with some embodiments. The p-channel stack further may include another GaN or InGaN layer over its polarization layer, with source/drain (S/D) portions adjacent the m-plane or a-plane sidewalls of that GaN or InGaN layer. The n-channel may include S/D portions over its GaN or InGaN layer, within its polarization layer, in accordance with some embodiments. Gate stack placement can be customized to provide any desired combination of enhancement and depletion modes for the resultant neighboring p-channel and n-channel transistor devices.

公开(公告)号：US10388777B2

公开(公告)日：2019-08-20

申请号：US15574817

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Robert S. Chau

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L21/02 ,  H01L21/8258 ,  H01L27/085 ,  H01L21/04 ,  H01L29/78

Abstract: Crystalline heterostructures including an elevated crystalline structure extending from one or more trenches in a trench layer disposed over a crystalline substrate are described. In some embodiments, an interfacial layer is disposed over a silicon substrate surface. The interfacial layer facilitates growth of the elevated structure from a bottom of the trench at growth temperatures that may otherwise degrade the substrate surface and induce more defects in the elevated structure. The trench layer may be disposed over the interfacial layer with a trench bottom exposing a portion of the interfacial layer. Arbitrarily large merged crystal structures having low defect density surfaces may be overgrown from the trenches. Devices, such as III-N transistors, may be further formed on the raised crystalline structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate.

公开(公告)号：US20190190489A1

公开(公告)日：2019-06-20

申请号：US16327712

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Sansaptak Dasgupta ,  Bruce A. Block ,  Paul B. Fischer ,  Han Wui Then ,  Marko Radosavljevic

IPC: H03H9/205 ,  H03H9/02

CPC classification number: H03H9/205 ,  H03H9/02007 ,  H03H9/02543 ,  H03H9/02574 ,  H03H9/13 ,  H03H9/15 ,  H03H9/172 ,  H03H2009/02173

Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices having multiple resonator thicknesses on a common substrate. A piezoelectric stack is formed in an STI trench and overgrown onto the STI material. In some cases, the piezoelectric stack can include epitaxially grown AlN. In some cases, the piezoelectric stack can include single crystal (epitaxial) AlN in combination with polycrystalline (e.g., sputtered) AlN. The piezoelectric stack thus forms a central portion having a first resonator thickness and end wings extending from the central portion having a different resonator thickness. Each wing may also have different thicknesses. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate. The end wings can have metal electrodes formed thereon, and the central portion can have a plurality of IDT electrodes patterned thereon.

公开(公告)号：US20190190488A1

公开(公告)日：2019-06-20

申请号：US16327705

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Sansaptak Dasgupta ,  Bruce A. Block ,  Paul B. Fischer ,  Han Wui Then ,  Marko Radosavljevic

IPC: H03H9/205 ,  H03H9/02

CPC classification number: H03H9/205 ,  H03H3/04 ,  H03H9/02007 ,  H03H9/175 ,  H03H2003/025 ,  H03H2003/0435 ,  H03H2009/02173

Abstract: Techniques are disclosed for forming integrated circuit film bulk acoustic resonator (FBAR) devices having multiple resonator thicknesses on a common substrate. A piezoelectric stack is formed in an STI trench and overgrown onto the STI material. In some cases, the piezoelectric stack can include epitaxially grown AlN. In some cases, the piezoelectric stack can include single crystal (epitaxial) AlN in combination with polycrystalline (e.g., sputtered) AlN. The piezoelectric stack thus forms a central portion having a first resonator thickness and end wings extending from the central portion and having a different resonator thickness. Each wing may also have different thicknesses from one another. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate. The end wings can have metal electrodes formed thereon, and the central portion can have a plurality of IDT electrodes patterned thereon.