公开(公告)号：US10453241B2

公开(公告)日：2019-10-22

申请号：US15477028

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Michael Apodaca ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Jonathan Kennedy ,  Slawomir Grajewski

IPC: G06T15/00 ,  G06T3/40

Abstract: A computing system to obtain an output includes a multi-plane rendering module includes a renderer receives a plurality of graphical objects to generate one or more image planes of object data, a resampler upscales lower resolution image planes to a higher resolution used by the output image, and a rasterizer combine pixels from a common location in the plurality of image planes after each image plane is upsampled to the higher resolution. The renderer receives one of the graphical objects having a location value along a z-axis of the scene, determines which of a plurality of image planes the graphical objects is located using the z-axis location for the graphical object, each of the planes possess a corresponding image resolution, and renders the graphical object into the image plane at the image resolution corresponding determined image plane.

公开(公告)号：US10417731B2

公开(公告)日：2019-09-17

申请号：US15494886

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/50 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F8/41

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type.

公开(公告)号：US20190251740A1

公开(公告)日：2019-08-15

申请号：US16215850

申请日：2018-12-11

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T15/50 ,  G06T15/80 ,  G06T15/00 ,  G06T17/20

CPC classification number: G06T15/503 ,  G06T15/005 ,  G06T15/80 ,  G06T17/205 ,  G06T2200/12

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

公开(公告)号：US10242494B2

公开(公告)日：2019-03-26

申请号：US15477016

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Devan Burke ,  Philip R. Laws ,  Subramanian Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle

IPC: G06F9/50 ,  G06T1/20 ,  G06T5/20 ,  G06T15/80

Abstract: An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.

公开(公告)号：US10242493B2

公开(公告)日：2019-03-26

申请号：US14319130

申请日：2014-06-30

Applicant: INTEL CORPORATION

Inventor： Gabor Liktor ,  Marco Salvi ,  Karthik Vaidyanathan

IPC: G06T15/00 ,  G06T15/04 ,  G06T15/80 ,  G06T1/20

Abstract: An apparatus and method for performing coarse pixel shading (CPS). For example, one embodiment of a method comprises: A method for coarse pixel shading (CPS) comprising: pre-processing a graphics mesh by creating a tangent-plane parameterization of desired vertex attributes for each vertex of the mesh; and performing rasterization of the mesh in a rasterization stage of a graphics pipeline using the tangent-plane parameterization.

公开(公告)号：US10152822B2

公开(公告)日：2018-12-11

申请号：US15477019

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer KP ,  Jonathan Kennedy ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Tomer Bar-On ,  Carsten Benthin ,  Adam T. Lake ,  Vasanth Ranganathan ,  Abhishek R. Appu

IPC: G06T15/08 ,  H04N5/369 ,  G02B27/01 ,  G06T15/10 ,  G06T15/60 ,  G06K9/00 ,  H04N5/232

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

公开(公告)号：US20180293760A1

公开(公告)日：2018-10-11

申请号：US15483701

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Hugues Labbe ,  Atsuo Kuwahara ,  Sameer Kp ,  Jonathan Kennedy ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh

IPC: G06T11/00 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06T11/001 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：US20180293699A1

公开(公告)日：2018-10-11

申请号：US15483837

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Abhishek Venkatesh ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.

公开(公告)号：US20180286112A1

公开(公告)日：2018-10-04

申请号：US15477015

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Altug Koker ,  Louis Feng ,  Tomasz Janczak ,  David M. Cimini ,  Karthik Vaidyanathan ,  Abhishek Venkatesh ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T15/40 ,  G06T15/80 ,  G06T15/00 ,  G06T17/20 ,  G06T15/06 ,  G06T1/20

CPC classification number: G06T15/405 ,  G06T1/20 ,  G06T15/005 ,  G06T15/06 ,  G06T15/30 ,  G06T15/80 ,  G06T17/20

Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.

公开(公告)号：US20170243395A1

公开(公告)日：2017-08-24

申请号：US15398111

申请日：2017-01-04

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Marco Salvi ,  Robert M. Toth

IPC: G06T15/50 ,  G06T1/20

CPC classification number: G06T15/503 ,  G06T1/20 ,  G06T2200/12

Abstract: In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. Examples where the shading rate may be reduced include areas where there is motion and camera defocus, areas of peripheral blur, and in general, any case where the visibility is reduced anyway. The shading rate may be changed in a region, such as a shading quad, by changing the size of the region.