公开(公告)号：US11768615B1

公开(公告)日：2023-09-26

申请号：US17739794

申请日：2022-05-09

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Ying Yu Tai

IPC: G06F3/00 ,  G06F3/06 ,  G06F1/20

CPC classification number: G06F3/0629 ,  G06F1/206 ,  G06F3/061 ,  G06F3/0673

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide adaptive media management based on temperature-related memory component capabilities. The controller can obtain a write temperature associated with an individual group of memory components. Based on the write temperature and a temperature threshold associated with the individual group of memory components, the controller can select an individual media management operation to perform.

公开(公告)号：US11763914B2

公开(公告)日：2023-09-19

申请号：US17557782

申请日：2021-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

IPC: G11C11/34 ,  G11C29/50 ,  G11C29/12 ,  G11C29/44 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C29/50004 ,  G11C16/10 ,  G11C16/26 ,  G11C29/12005 ,  G11C29/44

Abstract: A first sequence of operations corresponding to an error recovery process of a memory sub-system is determined. A value corresponding to an operating characteristic of a memory sub-system is determined, the operating characteristic corresponding to execution of a first sequence of operations of an error recovery process. A determination is made that the value satisfies a condition. In response to the value satisfying the first condition, a second sequence of operations corresponding to the error recovery process is executed.

公开(公告)号：US11742053B2

公开(公告)日：2023-08-29

申请号：US17467961

申请日：2021-09-07

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhongguang Xu ,  Zhenming Zhou

IPC: G11C29/50 ,  G11C29/12 ,  G06F11/10 ,  G06F11/07 ,  G11C29/44

CPC classification number: G11C29/50004 ,  G06F11/076 ,  G06F11/106 ,  G11C29/12005 ,  G11C29/44

Abstract: A value corresponding to an operating characteristic of a memory sub-system is determined. The value is compared to a threshold level to determine whether a condition is satisfied. In response to satisfying the condition, a read scrub operation associated with the memory sub-system is executed.

公开(公告)号：US11742029B2

公开(公告)日：2023-08-29

申请号：US17402279

申请日：2021-08-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhongguang Xu ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

IPC: G11C16/30 ,  G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C16/102 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3404

Abstract: A method includes performing a first write operation that writes data to a first memory unit of a group of memory units in a memory device, determining a write-to-write (W2W) delay based on a time difference between the first write operation and a second write operation on a memory unit in the group of memory units, wherein the second write operation occurred prior to the first write operation, identifying a threshold time criterion that is satisfied by the W2W delay, identifying a first read voltage level associated with the threshold time criterion, and associating the first read voltage level with a second memory unit of the group of memory units. The second memory unit can be associated with a second read voltage level that satisfies a selection criterion based on a comparison of the second read voltage level to the first read voltage level.

公开(公告)号：US20230207041A1

公开(公告)日：2023-06-29

申请号：US18117583

申请日：2023-03-06

Applicant: Micron Technology, Inc.

Inventor： Zhenlei Shen ,  Tingjun Xie ,  Zhenming Zhou

IPC: G11C29/42 ,  G06F11/10 ,  G06F3/06 ,  G11C13/00

CPC classification number: G11C29/42 ,  G06F11/1068 ,  G06F3/0619 ,  G06F3/0679 ,  G11C13/004 ,  G11C13/0069 ,  G06F3/0659 ,  G11C2029/0407

Abstract: A system includes a memory device having groups of managed units and a processing device coupled to the memory device. The processing device, during power on of the memory device, causes a read operation to be performed at a subset of a group of managed units and determines a bit error rate related to data read from the subset of the group of managed units. The bit error rate is a directional bit error rate resulting from an erroneously determined state compared to a programmed state that transitions between two opposing states. In response to the bit error rate satisfying a threshold criterion, the processing device causes a rewrite of the data stored at the group of managed units.

公开(公告)号：US20230207028A1

公开(公告)日：2023-06-29

申请号：US17580105

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Jian Huang ,  Zhenming Zhou ,  Murong Lang ,  Zhongguang Xu ,  Jiangli Zhu

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

CPC classification number: G11C16/3495 ,  G11C16/102 ,  G11C16/16 ,  G11C16/26

Abstract: A threshold criterion of a plurality of threshold criteria is identified based on a current program-erase cycle (PEC) count of a first block of a memory device, wherein the first block is configured as quad-level cell (QLC) memory. A raw bit error rate (RBER) associated with data of a second block of the memory device is determined, wherein the second block is configured as single-level cell (SLC) memory. It is determined that the RBER associated with the data of the second block satisfies the threshold criterion. In response to determining that the RBER satisfies the threshold criterion, the data of the second block is written to the first block.

公开(公告)号：US20230186995A1

公开(公告)日：2023-06-15

申请号：US17546425

申请日：2021-12-09

Applicant: Micron Technology, Inc.

Inventor： Jian Huang ,  Zhenming Zhou

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C29/44

CPC classification number: G11C16/102 ,  G11C16/26 ,  G11C16/08 ,  G11C29/4401 ,  G11C2029/1202

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a write operation to program first data to a first set of memory cells addressable by a first wordline of a first plurality of wordlines of a block of the memory device; performing a read operation on a second wordline of the plurality of wordlines, wherein the second wordline is adjacent to the first wordline; determining a number of bits programmed in a first logical level in the second wordline; and responsive to determining that the number of bits set satisfies a threshold criterion, copying second data from the first block to a second block.

公开(公告)号：US20230120838A1

公开(公告)日：2023-04-20

申请号：US18086580

申请日：2022-12-21

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhenming Zhou ,  Zhenlei Shen ,  Chih-Kuo Kao

IPC: G06F3/06 ,  G11C7/10

Abstract: A processing device in a memory sub-system initiates read operations on each of a plurality of segments in a first region of the memory device during a first time interval, wherein at least a subset of the plurality of segments in the first region of the memory device are storing host data. The processing device further receives, as a result of at least one read operation, at least one data signal from a corresponding one of the plurality of segments in the first region of the memory device, and performs a signal calibration operation using the at least one data signal to synchronize one or more relevant signals with a reference clock signal used by the processing device.

公开(公告)号：US20230090523A1

公开(公告)日：2023-03-23

申请号：US18071930

申请日：2022-11-30

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Tingjun Xie ,  Wei Wang ,  Frederick Adi ,  Zhenming Zhou ,  Jiangli Zhu

IPC: G06F3/06

Abstract: A current cycle count associated with a memory sub-system is determined. The current cycle count is compared to a set of cycle count threshold levels to determine a current lifecycle stage of the memory sub-system. A temperature associated with the memory sub-system is measured. The temperature is compared to a set of temperature levels to determine a current temperature level of the memory sub-system. A write-to-read delay time corresponding to the current lifecycle stage and the current temperature level is determined.

公开(公告)号：US11599272B2

公开(公告)日：2023-03-07

申请号：US17348226

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Seungjune Jeon ,  Zhenlei Shen

IPC: G06F3/06 ,  G06F12/10 ,  G06F7/58 ,  G06F12/02

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command specifying a logical address; determining a physical address associated with the logical address; determining a portion of the memory device that is referenced by the physical address; determine an endurance factor associated with the portion; and increasing, by a value derived from the endurance factor, a media management metric associated with a management unit of the memory device, wherein the management unit is referenced by the physical address.