Speed matching system for a web splicer mechanism in a web-fed printing press or the like
    87.
    发明授权
    Speed matching system for a web splicer mechanism in a web-fed printing press or the like 失效
    用于卷筒纸式印刷机等中的卷筒纸捻接机构的速度匹配系统

    公开(公告)号:US06695027B2

    公开(公告)日:2004-02-24

    申请号:US09994655

    申请日:2001-11-28

    Abstract: An apparatus splices a web of paper being paid out from a one web roll and fed into a printing press to another web roll being rotated in a splicing position. The new web roll of any diameter is spaced a prescribed distance from the old web traveling along a predefined path into the press. A sensor positioning mechanism adjustably moves a photoelectric web roll speed sensor along two orthogonal axes to an optimum sensing position with respect to the new web roll regardless of its diameter. An electronic control circuit has an input connected to a speed sensor for the old web traveling along the predefined path, and another to the photoelectric speed sensor for the new web roll, for energizing a new web roll drive motor according to a departure of the peripheral speed of the new web roll from the running speed of the old web.

    Abstract translation: 一个装置将从一个卷筒纸卷取出的纸幅卷起,并将其送入印刷机中,以便在拼接位置上旋转的另一卷筒卷筒纸。 任何直径的新卷筒纸与沿预定路线行进到印刷机中的旧纸幅间隔规定的距离。 传感器定位机构可以将光电卷筒纸速度传感器沿着两个正交轴线可调节地移动到相对于新卷筒纸卷筒的最佳感测位置,而不管其直径。 电子控制电路具有连接到用于沿着预定路径行进的旧纸幅的速度传感器的输入,另一个连接到用于新卷筒纸的光电速度传感器,用于根据外围设备的偏离来激励新的卷筒纸驱动电机 新网络卷的速度从旧网络的运行速度。

    Interconnect substrate and semiconductor device electronic instrument
    88.
    发明授权
    Interconnect substrate and semiconductor device electronic instrument 失效
    互连基板和半导体器件电子仪器

    公开(公告)号:US06670700B1

    公开(公告)日:2003-12-30

    申请号:US09807605

    申请日:2001-04-16

    Abstract: An interconnect substrate includes an upper substrate (30) on which an upper interconnect pattern (32) is formed, and a lower substrate (40) on which a lower interconnect pattern (42) is formed and to which the upper substrate (30) is adhered. The lower interconnect pattern (42) includes first lower land section (53) which are formed in the center portion of a first region (50) and are connected to the upper interconnect pattern (32), second lower land sections (64) which are formed in a second region (60) and are electrically connected to a second electronic chip, and lower connection sections (45) which run outside the center portion in the first region (50) than the center portion and connect the first lower land section (53) to the second lower land section (64).

    Abstract translation: 互连基板包括其上形成有上部布线图案(32)的上基板(30)和形成有下布线图案(42)的下基板(40),上基板(30) 坚持 下部布线图案(42)包括形成在第一区域(50)的中心部分并连接到上部布线图案(32)的第一下部陆部(53),第二下部陆地部分(64) 形成在第二区域(60)中并且电连接到第二电子芯片,以及下部连接部分(45),所述下部连接部分(45)在第一区域(50)的中心部分之外比中心部分延伸,并且连接第一下部陆部( 53)连接到第二下岸部(64)。

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