公开(公告)号：US20220173306A1

公开(公告)日：2022-06-02

申请号：US17134485

申请日：2020-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chun-Hsien Lin

IPC: H01L43/02 ,  H01L27/22

Abstract: A semiconductor device for internet of things (IoT) device includes a substrate having an array region defined thereon and a ring of dummy pattern surrounding the array region. Preferably, the ring of dummy pattern includes a plurality of magnetic tunneling junctions (MTJs) and a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region. The semiconductor device further includes a gap between the array region and the ring of dummy pattern.

公开(公告)号：US20220013715A1

公开(公告)日：2022-01-13

申请号：US16985206

申请日：2020-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wei Liu ,  Jia-Feng Fang ,  Chun-Hsien Lin

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

公开(公告)号：US20210043632A1

公开(公告)日：2021-02-11

申请号：US17079537

申请日：2020-10-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Chun-Hsien Lin ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L29/49

Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a first doped region in a substrate; removing part of the first doped region to form a trench in the substrate; forming a gate structure in the trench; and forming a barrier structure between the gate structure and the first doped region.

公开(公告)号：US10886395B2

公开(公告)日：2021-01-05

申请号：US16581750

申请日：2019-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/40 ,  H01L29/739

Abstract: A method for fabricating a tunnel field effect transistor (TFET) includes the steps of providing a substrate and then forming an interfacial layer on the substrate. Preferably, the step of forming the interfacial layer includes the steps of: performing a plasma treatment process to inject a first gas containing nitrogen; injecting a second gas containing oxygen; and injecting a precursor to react with the first gas and the second gas for forming the interfacial layer.

公开(公告)号：US10854520B2

公开(公告)日：2020-12-01

申请号：US16416279

申请日：2019-05-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Chun-Hsien Lin ,  Wei-Hao Huang ,  Kai-Teng Cheng

IPC: H01L21/8234 ,  H01L21/321 ,  H01L21/28 ,  H01L21/30 ,  H01L27/092 ,  H01L21/8238

Abstract: The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.

公开(公告)号：US10553534B2

公开(公告)日：2020-02-04

申请号：US15949084

申请日：2018-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Te Wei ,  Chun-Hsien Lin

IPC: H01L23/525 ,  H01L23/532 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/522

Abstract: A method for fabricating semiconductor device includes the steps of first forming a first dielectric layer on a substrate, in which a first conductor is embedded within the first dielectric layer. Next, a second dielectric layer is formed on the first dielectric layer, part of the second dielectric layer is removed to form a contact hole, and a lateral etching process is conducted to expand the contact hole to form a funnel-shaped opening. Next, a metal layer is formed in the funnel-shaped opening, and the metal layer is planarized to form a second conductor.

公开(公告)号：US10510884B2

公开(公告)日：2019-12-17

申请号：US16056564

申请日：2018-08-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78 ,  H01L29/49 ,  H01L21/3105

Abstract: A method for fabricating a semiconductor device is disclosed. A dummy gate is formed on a semiconductor substrate. The dummy gate has a first sidewall and a second sidewall opposite to the first sidewall. A low-k dielectric layer is formed on the first sidewall of the dummy gate and the semiconductor substrate. A spacer material layer is deposited on the low-k dielectric layer, the second sidewall of the dummy gate, and the semiconductor substrate. The spacer material layer and the low-k dielectric layer are etched to form a first spacer structure on the first sidewall and a second spacer structure on the second sidewall. A drain doping region is formed in the semiconductor substrate adjacent to the first spacer structure. A source doping region is formed in the semiconductor substrate adjacent to the second spacer structure.

公开(公告)号：US10199277B2

公开(公告)日：2019-02-05

申请号：US15268630

申请日：2016-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Kuo Chiang ,  Chun-Hsien Lin

IPC: H01L21/8232 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/423 ,  H01L29/51 ,  H01L27/092

Abstract: A semiconductor structure includes a stacked metal oxide layer on a substrate, wherein the stacked metal oxide layer includes a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer from top to bottom, and the energy bandgap of the second metal oxide layer is lower than the energy bandgap of the first metal oxide layer and that of the third metal oxide layer. The semiconductor structure includes a metal oxide layer on a substrate, wherein the energy bandgap of the metal oxide layer changes along a direction perpendicular to the surface of the substrate. The present invention also provides a semiconductor process forming said semiconductor structure.

公开(公告)号：US20180233449A1

公开(公告)日：2018-08-16

申请号：US15949084

申请日：2018-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Te Wei ,  Chun-Hsien Lin

IPC: H01L23/525 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L21/033 ,  H01L21/8234

CPC classification number: H01L23/5256 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/76804 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53295

Abstract: A method for fabricating semiconductor device includes the steps of first forming a first dielectric layer on a substrate, in which a first conductor is embedded within the first dielectric layer. Next, a second dielectric layer is formed on the first dielectric layer, part of the second dielectric layer is removed to form a contact hole, and a lateral etching process is conducted to expand the contact hole to form a funnel-shaped opening. Next, a metal layer is formed in the funnel-shaped opening, and the metal layer is planarized to form a second conductor.

公开(公告)号：US09875901B2

公开(公告)日：2018-01-23

申请号：US14941648

申请日：2015-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Tai Chiang ,  Chun-Hsien Lin

IPC: H01L29/76 ,  H01L21/285 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28518 ,  H01L21/28008 ,  H01L21/76804 ,  H01L21/76814 ,  H01L29/41725 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A manufacturing method of MOS transistor, the MOS transistor includes a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface and a curved top surface, both the curved top surface and the curved bottom surface bend toward the substrate and the curved top surface is sunken from two sides thereof, two ends of the silicide layer point tips raised up over the source/drain region and the silicide layer in the middle is thicker than the silicide layer in the peripheral, thereby forming a crescent structure. The present invention further provides a manufacturing method of the MOS transistor.