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公开(公告)号:US20210005662A1
公开(公告)日:2021-01-07
申请号:US16531108
申请日:2019-08-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Kun-Ju Li , Tai-Cheng Hou , Hsin-Jung Liu , Fu-Yu Tsai , Bin-Siang Tsai , Chau-Chung Hou , Yu-Lung Shih , Ang Chan , Chih-Yueh Li , Chun-Tsen Lu
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.
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公开(公告)号:US20200266095A1
公开(公告)日:2020-08-20
申请号:US16866360
申请日:2020-05-04
Applicant: United Microelectronics Corp.
Inventor: Da-Jun Lin , Bin-Siang Tsai , Chich-Neng Chang
IPC: H01L21/768 , H01L23/528 , H01L23/532 , H01L23/522
Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. A porous dielectric layer is disposed over the substrate, sealing the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.
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公开(公告)号:US20200258771A1
公开(公告)日:2020-08-13
申请号:US16858698
申请日:2020-04-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Yu-Cheng Lin , Chich-Neng Chang , Bin-Siang Tsai
IPC: H01L21/768 , H01L23/522
Abstract: A method of forming an interconnection structure is disclosed, including providing a substrate, forming a patterned layer on the substrate, the patterned layer comprising at least a trench formed therein, depositing a first dielectric layer on the patterned layer and sealing an air gap in the trench, depositing a second dielectric layer on the first dielectric layer and completely covering the patterned layer, and performing a curing process to the first dielectric layer and the second dielectric layer.
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公开(公告)号:US20200185325A1
公开(公告)日:2020-06-11
申请号:US16212401
申请日:2018-12-06
Applicant: United Microelectronics Corp.
Inventor: Da-Jun Lin , Bin-Siang Tsai , San-Fu Lin
IPC: H01L23/532 , H01L23/528 , H01L21/764 , H01L21/768
Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. At least two metal elements are formed in the dielectric layer, wherein an air gap is between adjacent two of the metal elements. A cap layer is disposed over the substrate, wherein a portion of the cap layer above the adjacent two of the metal elements has a hydrophilic surface. An inter-layer dielectric layer is disposed on the cap layer. The inter-layer dielectric layer seals the air gap between the two metal elements. The air gap remains and extends higher than a top surface of the metal elements.
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公开(公告)号:US10665546B1
公开(公告)日:2020-05-26
申请号:US16212401
申请日:2018-12-06
Applicant: United Microelectronics Corp.
Inventor: Da-jun Lin , Bin-Siang Tsai , San-Fu Lin
IPC: H01L21/764 , H01L21/768 , H01L21/02 , H01L23/532 , H01L23/528
Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. At least two metal elements are formed in the dielectric layer, wherein an air gap is between adjacent two of the metal elements. A cap layer is disposed over the substrate, wherein a portion of the cap layer above the adjacent two of the metal elements has a hydrophilic surface. An inter-layer dielectric layer is disposed on the cap layer. The inter-layer dielectric layer seals the air gap between the two metal elements. The air gap remains and extends higher than a top surface of the metal elements.
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公开(公告)号:US10186453B2
公开(公告)日:2019-01-22
申请号:US14738943
申请日:2015-06-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Wei-Hsin Liu , Bin-Siang Tsai
IPC: H01L21/768 , H01L23/522 , H01L21/02 , H01L21/311 , H01L21/32 , H01L23/532 , H01L21/3105 , H01L23/485
Abstract: A semiconductor process includes the following steps. Metal patterns are formed on a first dielectric layer. A modifiable layer is formed to cover the metal patterns and the first dielectric layer. A modification process is performed to modify a part of the modifiable layer on top sides of the metal patterns, thereby top masks being formed. A removing process is performed to remove a part of the modifiable layer on sidewalls of the metal patterns but preserve the top masks. A dielectric layer having voids under the top masks and between the metal patterns is formed. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.
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公开(公告)号:US20180331044A1
公开(公告)日:2018-11-15
申请号:US15624498
申请日:2017-06-15
Applicant: United Microelectronics Corp.
Inventor: Yi-Yu Wu , Chun-Yuan Wu , Chih-Chien Liu , Bin-Siang Tsai
IPC: H01L23/532 , H01L23/528 , H01L23/522 , H01L21/02 , H01L21/768
CPC classification number: H01L23/53257 , H01L21/02068 , H01L21/02164 , H01L21/02175 , H01L21/02244 , H01L21/02252 , H01L21/76883 , H01L23/5226 , H01L23/5283 , H01L23/53228 , H01L23/53266 , H01L23/53295
Abstract: A semiconductor device including a tungsten contact structure formed in a first dielectric layer on a substrate is provided. The tungsten contact structure contains a seam structure. A tungsten oxide layer is formed at least on a sidewall of the seam structure.
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公开(公告)号:US09917007B2
公开(公告)日:2018-03-13
申请号:US15188621
申请日:2016-06-21
Applicant: United Microelectronics Corp.
Inventor: Yi-Yu Wu , Bin-Siang Tsai
IPC: H01L21/768 , H01L21/311 , H01L21/033
CPC classification number: H01L21/76816 , H01L21/0332 , H01L21/31111 , H01L21/31116 , H01L21/31144
Abstract: A method of forming an opening pattern including the following steps is provided. An ultra low dielectric constant layer, a dielectric hard mask layer and a patterned metal hard mask layer are sequentially formed on a substrate. A portion of the dielectric hard mask layer is removed to form a patterned dielectric hard mask layer by using the patterned metal hard mask layer as a mask. The patterned metal hard mask layer is removed after forming the patterned dielectric hard mask layer. A portion of the ultra low dielectric constant layer is removed to form a first opening by using the patterned dielectric hard mask layer as a mask.
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公开(公告)号:US20250112184A1
公开(公告)日:2025-04-03
申请号:US18979653
申请日:2024-12-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Da-Jun Lin , Bin-Siang Tsai , Fu-Yu Tsai
IPC: H01L23/00
Abstract: A semiconductor device includes an aluminum (Al) pad on a substrate, a wire bonded onto the Al pad, a cobalt (Co) layer between and directly contacting the Al pad and the wire, and a Co—Pd alloy on the Al pad and divide the Co layer into a first portion, a second portion, and a third portion. Preferably, the wire includes a copper (Cu) wire and a palladium (Pd) layer coated on the Cu wire.
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公开(公告)号:US20250040158A1
公开(公告)日:2025-01-30
申请号:US18233899
申请日:2023-08-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Da-Jun Lin , Bin-Siang Tsai , Fu-Yu Tsai , Chung-Yi Chiu
IPC: H10K10/10
Abstract: A metal-insulator-metal capacitor includes a bottom electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and a top electrode stacked from bottom to top. The superlattice layer contacts the dielectric layer. A silicon dioxide layer has a negative voltage coefficient of capacitance.
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