公开(公告)号：US11721591B2

公开(公告)日：2023-08-08

申请号：US17338666

申请日：2021-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.

公开(公告)号：US20230215855A1

公开(公告)日：2023-07-06

申请号：US17673749

申请日：2022-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Chien-Ting Lin ,  Yu-Hsiang Lin ,  Ssu-I Fu ,  Chih-Kai Hsu

IPC: H01L25/18 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L25/50 ,  H01L25/0657 ,  H01L24/08

Abstract: A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

公开(公告)号：US20230197710A1

公开(公告)日：2023-06-22

申请号：US17585582

申请日：2022-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin ,  Chia-Jung Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen

IPC: H01L27/02 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L29/41791 ,  H01L29/7851 ,  H01L29/66795 ,  H01L29/0653

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

公开(公告)号：US20230047580A1

公开(公告)日：2023-02-16

申请号：US17403578

申请日：2021-08-16

Applicant: United Microelectronics Corp.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A high voltage transistor structure including a substrate, a first isolation structure, a second isolation structure, a gate structure, a first source and drain region, and a second source and drain region is provided. The first isolation structure and the second isolation structure are disposed in the substrate. The gate structure is disposed on the substrate, at least a portion of the first isolation structure, and at least a portion of the second isolation structure. The first source and drain region and the second source and drain region are located in the substrate on two sides of the first isolation structure and the second isolation structure. The depth of the first isolation structure is greater than the depth of the second isolation structure.

公开(公告)号：US20230037410A1

公开(公告)日：2023-02-09

申请号：US17406028

申请日：2021-08-18

Applicant: United Microelectronics Corp.

Inventor： Chun-Ya Chiu ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chin-Hung Chen ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/66

Abstract: A high voltage transistor structure including a substrate, a first drift region, a second drift region, a first cap layer, a second cap layer, a gate structure, a first source and drain region, and a second source and drain region is provided. The first and second drift regions are disposed in the substrate. The first and second cap layers are respectively disposed on the first and second drift regions. The gate structure is disposed on the substrate and located over at least a portion of the first drift region and at least a portion of the second drift region. The first and second source and drain regions are respectively disposed in the first and second drift regions and located on two sides of the gate structure. The size of the first drift region and the size of the second drift region are asymmetric.

公开(公告)号：US20210366913A1

公开(公告)日：2021-11-25

申请号：US16905883

申请日：2020-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Chien-Hung Chen

IPC: H01L27/11

Abstract: A static random access memory (SRAM) includes a substrate having a first active region and a second active region adjacent to the first active region. A first gate structure is disposed on the substrate and across the first active region and the second active region. A second gate structure is adjacent to a first side of the first gate structure. A first lower contact structure is disposed on the first active region and adjacent to a second side of the first gate structure. A first upper contact structure is disposed on and in direct contact with the first lower contact structure. A top surface of the first lower contact structure and a sidewall of the first upper contact structure comprise a step profile therebetween.

公开(公告)号：US11145733B1

公开(公告)日：2021-10-12

申请号：US17033919

申请日：2020-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Hung Chen ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Chia-Jung Hsu ,  Chun-Ya Chiu ,  Yu-Hsiang Lin ,  Po-Wen Su ,  Chung-Fu Chang ,  Guang-Yu Lo ,  Chun-Tsen Lu

IPC: H01L29/423 ,  H01L29/40 ,  H01L21/308 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L29/78

Abstract: The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.

公开(公告)号：US20210296183A1

公开(公告)日：2021-09-23

申请号：US17338696

申请日：2021-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, and a metal gate adjacent to the isolation structure. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

公开(公告)号：US20210050255A1

公开(公告)日：2021-02-18

申请号：US16569544

申请日：2019-09-12

Applicant: United Microelectronics Corp.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chia-Jung Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/768 ,  H01L27/108

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. The substrate includes a pixel region having a first conductive region and a logic region having a second conductive region. A dielectric layer is formed on the substrate to cover the first conductive region. A first contact opening is formed in the dielectric layer to expose the first conductive region. A doped polysilicon layer is sequentially formed in the first contact opening. A first metal silicide layer is formed on the doped polysilicon layer. A second contact opening is formed in the dielectric layer to expose the second conductive region. A barrier layer and a metal layer are respectively formed in the first contact opening and the second contact opening.

公开(公告)号：US10755919B2

公开(公告)日：2020-08-25

申请号：US16273003

申请日：2019-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chi-Ting Wu ,  Yu-Hsiang Lin

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/78 ,  H01L21/67 ,  H01L29/165 ,  H01L29/66 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/51

Abstract: A method of manufacturing semiconductor devices, including the steps of providing a substrate with a first active region, a second active region and a third active region, forming dummy gates in the first active region, the second active region and the third active region, removing the dummy gates to form trenches in the first active region, the second active region and the third active region, forming a high-k dielectric layer, a first bottom barrier metal layer on the high-k dielectric layer, a second bottom barrier metal layer on the first bottom barrier metal layer, and a first work function metal layer on the second bottom barrier metal layer in the trenches, removing the first work function metal layer from the second active region and the third active region, removing the second bottom barrier metal layer from the third region, and filling up each trench with a low resistance metal.