公开(公告)号：US20240347503A1

公开(公告)日：2024-10-17

申请号：US18201976

申请日：2023-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shing-Ren SHEU ,  Kai-Kuang HO ,  Yu-Jie LIN ,  Kuo-Ming CHEN ,  Yi-Feng HSU

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/94 ,  H01L23/49816 ,  H01L24/04 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/13023 ,  H01L2224/48453 ,  H01L2224/73207 ,  H01L2224/94

Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a first chip, a second chip and a conductive structure. The first chip has an active side and an opposite side disposed opposite to each other. The second chip includes a chip bonding portion and an outer pad, and the outer pad is located outside the chip bonding portion. The first chip is disposed on the chip bonding portion of the second chip with the active side. The conductive structure is disposed on the outer pad, and the conductive structure includes a stack of a plurality of metal balls. The stack extends from the outer pad beyond the opposite side of the first chip.

公开(公告)号：US20240347459A1

公开(公告)日：2024-10-17

申请号：US18317117

申请日：2023-05-15

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou ,  Ding Lung Chen

IPC: H01L23/528

CPC classification number: H01L23/5286

Abstract: Provided is a semiconductor including a substrate, a semiconductor element disposed on the substrate, an interconnect structure, first and second power deliver lines, and first and second power deliver network (PDN) structures. The interconnect structure is disposed in the element region, above the semiconductor element, and electrically connected with the semiconductor element. The first and the second power deliver lines are disposed above the interconnect structure and electrically connected to the first and the second power supplies, respectively. The first PDN structure is disposed between the substrate and the first power deliver line, and connected to the first power deliver line and a lowest circuit layer of the interconnect structure. The second PDN structure is disposed between the substrate and the second power deliver line, and connected to the second power deliver line and the lowest circuit layer of the interconnect structure.

公开(公告)号：US20240347338A1

公开(公告)日：2024-10-17

申请号：US18755651

申请日：2024-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L21/02 ,  H01L21/8258 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/02565 ,  H01L21/8258 ,  H01L29/66969 ,  H01L29/7869

Abstract: The present invention provides a semiconductor structure, including a substrate, a thin-film transistor (TFT) on the substrate, wherein the thin-film transistor including a TFT channel layer, a first source and a first drain in the TFT channel layer and a first capping layer on the TFT channel layer. A MOSFET is on the substrate, with a second gate, a second source and a second drain on two sides of the second gate and a second capping layer on the second gate, wherein top surfaces of the second capping layer and the first capping layer are leveled, and a first ILD layer is on the first capping layer and the second capping layer, wherein the first ILD layer and the first capping layer function collectively as a gate dielectric layer for the TFT.

公开(公告)号：US12120962B2

公开(公告)日：2024-10-15

申请号：US18504176

申请日：2023-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Da-Jun Lin ,  Chau-Chung Hou ,  Wei-Xin Gao

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

公开(公告)号：US20240339495A1

公开(公告)日：2024-10-10

申请号：US18195354

申请日：2023-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/66545

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor channel layer, a second semiconductor channel layer, and an isolation structure. The first semiconductor channel layer, the second semiconductor channel layer, and the isolation structure are disposed above the semiconductor substrate. The isolation structure includes a vertical portion, a first horizontal portion, and a second horizontal portion. The vertical portion is disposed between the first semiconductor channel layer and the second semiconductor channel layer in a horizontal direction. The first horizontal portion is disposed between the first semiconductor channel layer and the semiconductor substrate in a vertical direction. The second horizontal portion is disposed between the second semiconductor channel layer and the semiconductor substrate in the vertical direction. The first horizontal portion and the second horizontal portion are connected with the vertical portion.

公开(公告)号：US20240332421A1

公开(公告)日：2024-10-03

申请号：US18227979

申请日：2023-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/66795

Abstract: A semiconductor device includes a first fin structure, an insulating structure, a first groove and a gate structure. The first fin structure is extended along a first direction on a substrate. The insulating structure surrounds the first fin structure. The first groove is extended along the first direction and disposed between the first fin structure and the insulating structure. The first groove exposes a first portion of the substrate. The gate structure is extended along a second direction on the first fin structure. At least a portion of the gate structure is disposed in the first groove. The gate structure includes a gate dielectric layer disposed on the first fin structure and the first portion of the substrate.

公开(公告)号：US20240332067A1

公开(公告)日：2024-10-03

申请号：US18739344

申请日：2024-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yunfei Li ,  Ji Feng ,  Guohai Zhang ,  Ching Hwa Tey

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/7682 ,  H01L21/02063 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535

Abstract: A transistor structure with an air gap includes a substrate. A transistor is disposed on the substrate. An etching stop layer covers and contacts the transistor and the substrate. A first dielectric layer covers and contacts the etching stop layer. A second dielectric layer covers the first dielectric layer. A trench is disposed on the gate structure and within the first dielectric layer and the second dielectric layer. A width of the trench within the second dielectric layer is smaller than a width of the trench within the first dielectric layer. A filling layer is disposed within the trench and covers the top surface of the second dielectric layer. An air gap is formed within the filling layer.

公开(公告)号：US20240332066A1

公开(公告)日：2024-10-03

申请号：US18136888

申请日：2023-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chih-Wei Chang ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76832 ,  H01L23/53238

Abstract: A semiconductor structure includes a substrate; a first dielectric layer on the substrate; an etch stop layer on the first dielectric layer; a second dielectric layer on the etch stop layer; a first conductor and a second conductor in the second dielectric layer, an air gap in the second dielectric layer and between the first conductor and the second conductor; and a low-polarity dielectric layer on a sidewall surface of the second dielectric layer within the air gap.

公开(公告)号：US12108680B2

公开(公告)日：2024-10-01

申请号：US18135758

申请日：2023-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Yu-Ping Wang

IPC: H10N50/01 ,  H10N50/80 ,  H10B61/00 ,  H10N50/85

CPC classification number: H10N50/01 ,  H10N50/80 ,  H10B61/00 ,  H10N50/85

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.

公开(公告)号：US12107164B2

公开(公告)日：2024-10-01

申请号：US17672733

申请日：2022-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Jhe Hsu ,  Che-Yi Ho

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/165

Abstract: A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, a second buffer layer on the first buffer layer, a bulk layer on the second buffer layer, a first cap layer on the bulk layer, and a second cap layer on the first cap layer. Preferably, the bottom surface of the first buffer layer includes a linear surface, a bottom surface of the second buffer layer includes a curve, and the second buffer layer includes a linear sidewall.