公开(公告)号：US06765300B1

公开(公告)日：2004-07-20

申请号：US09890575

申请日：2002-02-11

Applicant: Dirk Wagenaar ,  Kay Krupka ,  Helmut Schlaak ,  Uppili Sridhar ,  Victor D. Samper ,  Pang Dow Foo

Inventor： Dirk Wagenaar ,  Kay Krupka ,  Helmut Schlaak ,  Uppili Sridhar ,  Victor D. Samper ,  Pang Dow Foo

IPC: H01L2348

CPC classification number: B81C1/00666 ,  B81C2201/0167 ,  H01H59/0009 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A microstructure relay is provided, having a body that includes upper and lower portions. The lower portion is formed from a substrate, and the upper portion is formed on the substrate to avoid bonding of the lower portion to the upper portion. A support member is fixed to the body at a first end of the support member to form a cantilever, wherein an upper surface of the support member and a lower surface of the upper portion of the body form a cavity. A first contact region is located on the upper surface at a second end of the support member. The first contact region comprises a first contact, wherein pivoting the support member toward the lower surface causes the first contact to be electrically coupled to a counter contact.

Abstract translation: 提供一种微结构继电器，其具有包括上部和下部的主体。 下部由基板形成，上部形成在基板上，以避免下部与上部的接合。 支撑构件在支撑构件的第一端处固定到主体以形成悬臂，其中支撑构件的上表面和主体的上部的下表面形成空腔。 第一接触区域位于支撑构件的第二端的上表面上。 第一接触区域包括第一触点，其中支撑构件向下表面转动使得第一接触件电耦合到反接触。

公开(公告)号：US20040132227A1

公开(公告)日：2004-07-08

申请号：US10337011

申请日：2003-01-06

Inventor： Robert D. Horning ,  McDonald Robinson ,  Timothy Louis Scullard

IPC: H01L021/00

CPC classification number: B81C1/00666 ,  B81C2201/0167 ,  Y10T74/12

Abstract: A method for controlling bow in wafers which utilize doped layers is described. The method includes depositing a silicon-germanium layer onto a substrate, depositing an undoped buffer layer onto the silicon-germanium layer, and depositing a silicon-boron layer onto the undoped layer.

Abstract translation: 描述了一种利用掺杂层在晶片中控制弓形的方法。 该方法包括将硅 - 锗层沉积到衬底上，将未掺杂的缓冲层沉积到硅 - 锗层上，以及在未掺杂的层上沉积硅 - 硼层。

公开(公告)号：US06759261B2

公开(公告)日：2004-07-06

申请号：US09556795

申请日：2000-04-25

Applicant: Akira Shimokohbe ,  Seiichi Hata

Inventor： Akira Shimokohbe ,  Seiichi Hata

IPC: H01L2100

CPC classification number: B81C1/00682 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81C2201/0167

Abstract: A thin film made of an amorphous material having supercooled liquid phase region is formed on a substrate. Then, the thin film is heated to a temperature within the supercooled liquid phase region and is deformed by its weight, mechanical external force, electrostatic external force or the like, thereby to form a thin film-structure. Thereafter, the thin film-structure is cooled down to room temperature, which results in the prevention of the thin film's deformation.

Abstract translation: 在基板上形成由具有过冷液相区域的无定形材料制成的薄膜。 然后，将薄膜加热至过冷液相区域内的温度，并通过其重量，机械外力，静电外力等变形，从而形成薄膜结构。 此后，将薄膜结构冷却至室温，从而防止薄膜的变形。

公开(公告)号：US06730615B2

公开(公告)日：2004-05-04

申请号：US10079614

申请日：2002-02-19

Applicant: Michael Goldstein

Inventor： Michael Goldstein

IPC: H01L2131

CPC classification number: B81C1/00666 ,  B81B2201/042 ,  B81C2201/0167 ,  G02B5/0833 ,  G02B26/0833 ,  Y10S438/954

Abstract: An optical device having a high reflector tunable stress coating includes a micro-electromechanical system (MEMS) platform, a mirror disposed on the MEMS platform, and a multiple layer coating disposed on the mirror. The multiple layer coating includes a layer of silver (Ag), a layer of silicon dioxide (SiO2) deposited on the layer of Ag, a layer of intrinsic silicon (Si) deposited on the layer of SiO2, and a layer of silicon oxynitride (SiOxNy) deposited on the layer of Si. The concentration of nitrogen is increased and/or decreased to tune the stress (e.g., tensile, none, compressive).

公开(公告)号：US20040018749A1

公开(公告)日：2004-01-29

申请号：US10190133

申请日：2002-07-08

Inventor： Benjamin F. Dorfman

IPC: H01L021/469 ,  H01L021/31

CPC classification number: B81C1/00666 ,  B81C2201/0167 ,  C30B33/00 ,  H01L21/302

Abstract: A method for decreasing brittleness of single crystals, semiconductor wafers and fragile elements of structures and devices is invented. The method is based on applying to the crystal surface a hard amorphous stabilized carbon low-stress coating possessing adhesion to the substrate that is equal to or exceeding the tensile strength of the protected crystalline material. The carbon coating is stabilized with at least two alloying elements: the first alloying element is selected from the group consisting of O, H, N, or their combinations; the second alloying element is selected from the group consisting of Si, B, transition metals, or their combinations. According to the invented method, the most effective structure of SinullO-stabilized hard amorphous carbon is graphite-likenulldiamond-like composite of atomic scale named QUASAM. Also according to the present invention, the diamond-likenullquartz-like composite of atomic scale named DLN (American trade mark is DYLYN) may be applied to the crystalline structures, while the QUASAM coatings are still the most preferable ones. In accordance with the present invention, the thickness of coatings increasing the flexibility of single crystal structures are typically in the thickness range of 0.1 micrometers to 10 micrometers, while the thickness range of 0.20 to 2.5 micrometers is more preferable one in many cases, and the thickness range of 0.30 to 1.5 micrometers is still more preferable for silicon wafers, while the range of 0.35 to 1.0 micrometers is the most preferable one. Also in accordance with the present invention, the multi-layer coatings and/or functionally graded coatings may be applied to increase the fracture toughness of crystalline materials or functional structures, while the first protective layer possesses the above indicated adhesion, mechanical properties and thickness. The results of extensive tests over 200 samples of protected silicon wafers are provided. Application of 0.35 to 1 micrometers thick coatings resulted with the 2 to 3-fold increase of critical angle of bending, while no one of the coated samples had been fractured at the bending angle lesser than the average value of uncoated wafers.

公开(公告)号：US20030155632A1

公开(公告)日：2003-08-21

申请号：US10079614

申请日：2002-02-19

Inventor： Michael Goldstein

IPC: H01L023/58 ,  H01L021/31

CPC classification number: B81C1/00666 ,  B81B2201/042 ,  B81C2201/0167 ,  G02B5/0833 ,  G02B26/0833 ,  Y10S438/954

Abstract: An optical device having a high reflector tunable stress coating includes a micro-electromechanical system (MEMS) platform, a mirror disposed on the MEMS platform, and a multiple layer coating disposed on the mirror. The multiple layer coating includes a layer of silver (Ag), a layer of silicon dioxide (SiO2) deposited on the layer of Ag, a layer of intrinsic silicon (Si) deposited on the layer of SiO2, and a layer of silicon oxynitride (SiOxNy) deposited on the layer of Si. The concentration of nitrogen is increased and/or decreased to tune the stress (e.g., tensile, none, compressive).

Abstract translation: 具有高反射器可调应力涂层的光学装置包括微机电系统（MEMS）平台，设置在MEMS平台上的反射镜和设置在反射镜上的多层涂层。 多层涂层包括银（Ag）层，沉积在Ag层上的二氧化硅（SiO 2）层，沉积在SiO 2层上的本征硅（Si）层和氮氧化硅层 SiO x N y）沉积在Si层上。 氮的浓度增加和/或降低以调节应力（例如，拉伸，无，压缩）。

公开(公告)号：US20020186444A1

公开(公告)日：2002-12-12

申请号：US10207537

申请日：2002-07-29

Inventor： David Alan Koester

IPC: G02B026/08

CPC classification number: B81B3/0072 ,  B81B2201/045 ,  B81C2201/0167 ,  G02B26/0866

Abstract: A microelectronic reflector is fabricated by forming a first polysilicon layer on a microelectronic substrate, forming a first phosphosilicate glass (PSG) layer on the first polysilicon layer, and reactive ion etching to remove the first PSG layer from at least a portion of the first polysilicon layer. A second polysilicon layer is formed on at least a portion of the first polysilicon layer from which the first PSG layer was removed and a second PSG layer is formed on at least a second portion of the second polysilicon layer. Reactive ion etching is performed to remove the second PSG layer from at least a portion of the second polysilicon layer. A third PSG layer then is formed on at least a portion of the second polysilicon layer from which the second PSG layer was removed. Reactive ion etching is performed to remove the third PSG layer from at least a portion of the second polysilicon layer. By forming a third PSG layer, and reactive ion etching this layer, additional stress may be created in the first and/or second doped polysilicon layers that bends the ends of the doped first and/or second polysilicon layers towards the microelectronic substrate upon release of the treated polysilicon layer from the substrate, compared to doped polysilicon layers on which the third PSG layer was not formed and reactive ion etched. This increased stress may be counteracted by forming a stress-correcting layer on at least a portion of the second polysilicon layer from which the third PSG layer was removed, and then forming a reflective layer such as gold on at least a portion of the stress-correcting layer. The stress-correcting layer preferably comprises platinum, which can produce high stresses that can counteract the stresses in the first and second doped polysilicon layers, to thereby allow a flat mirror and/or beam to be produced.

Abstract translation: 通过在微电子衬底上形成第一多晶硅层，在第一多晶硅层上形成第一磷硅酸盐玻璃（PSG）层，以及反应离子刻蚀以从第一多晶硅层的至少一部分去除第一PSG层来制造微电子反射体 层。 在去除第一PSG层的第一多晶硅层的至少一部分上形成第二多晶硅层，并且在第二多晶硅层的至少第二部分上形成第二PSG层。 执行反应离子蚀刻以从第二多晶硅层的至少一部分去除第二PSG层。 然后在去除第二PSG层的第二多晶硅层的至少一部分上形成第三PSG层。 执行反应离子蚀刻以从第二多晶硅层的至少一部分去除第三PSG层。 通过形成第三PSG层和反应离子蚀刻该层，可以在第一和/或第二掺杂多晶硅层中产生额外的应力，该第一和/或第二掺杂多晶硅层在释放时折射掺杂的第一和/或第二多晶硅层的端部朝向微电子衬底 与其上未形成第三PSG层的反射离子蚀刻的掺杂多晶硅层相比，来自衬底的处理过的多晶硅层。 这种增加的应力可以通过在去除第三PSG层的第二多晶硅层的至少一部分上形成应力校正层，然后在至少一部分应力层上形成反射层，例如金， 校正层。 应力校正层优选地包括铂，其可以产生可以抵消第一和第二掺杂多晶硅层中的应力的高应力，从而允许产生平坦的反射镜和/或光束。

公开(公告)号：US5922212A

公开(公告)日：1999-07-13

申请号：US663001

申请日：1996-06-07

Applicant: Kazuhiko Kano ,  Kenichi Nara ,  Toshimasa Yamamoto ,  Nobuyuki Kato ,  Yoshitaka Gotoh ,  Yoshinori Ohtsuka ,  Kenichi Ao

Inventor： Kazuhiko Kano ,  Kenichi Nara ,  Toshimasa Yamamoto ,  Nobuyuki Kato ,  Yoshitaka Gotoh ,  Yoshinori Ohtsuka ,  Kenichi Ao

IPC: B81B3/00 ,  B81C1/00 ,  G01P15/08 ,  G01P15/125 ,  C23F1/00

CPC classification number: G01P15/125 ,  B81B3/0072 ,  B81C1/00666 ,  G01P15/0802 ,  B81C2201/0164 ,  B81C2201/0167 ,  B81C2201/017 ,  G01P2015/0814

Abstract: A semiconductor sensor having a thin-film structure body, in which thin-film structure is prevented from bending due to the internal stress distribution in the thickness direction, is disclosed. A silicon-oxide film is formed as a sacrificial layer on a silicon substrate, and a polycrystalline-silicon thin film is formed on the silicon-oxide film. Thereafter, phosphorus (P) is ion-implanted in the surface of the polycrystalline-silicon thin film, and thereby the surface state of the polycrystalline-silicon thin film is modified. A portion of distribution of stress existing in the thickness direction of the polycrystalline-silicon thin film is changed by this modification, and stress distribution is adjusted. By removal of the silicon-oxide film, a movable member of the polycrystalline-silicon thin film is disposed above the silicon substrate with a gap interposed therebetween.

Abstract translation: 公开了一种具有薄膜结构体的半导体传感器，其薄膜结构被防止由于厚度方向上的内部应力分布而弯曲。 在硅衬底上形成氧化硅膜作牺牲层，在氧化硅膜上形成多晶硅薄膜。 此后，将磷（P）离子注入多晶硅薄膜的表面，从而改变多晶硅薄膜的表面状态。 通过该变形例改变在多晶硅薄膜的厚度方向上存在的应力分布的一部分，并且调整应力分布。 通过去除氧化硅膜，多晶硅薄膜的可移动部件设置在硅衬底之上，其间插入间隙。

公开(公告)号：US11785852B2

公开(公告)日：2023-10-10

申请号：US17979783

申请日：2022-11-03

Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR SINGAPORE PTE. LTD.

Inventor： You Qian ,  Joan Josep Giner De Haro ,  Rakesh Kumar

IPC: H10N30/067 ,  H10N30/073 ,  H04R17/02 ,  H10N30/08 ,  H10N30/87 ,  H10N30/00 ,  H10N30/06

CPC classification number: H10N30/067 ,  H04R17/02 ,  H10N30/06 ,  H10N30/073 ,  H10N30/08 ,  H10N30/1051 ,  H10N30/872 ,  B81B2201/0257 ,  B81C2201/013 ,  B81C2201/016 ,  B81C2201/019 ,  B81C2201/0167

Abstract: A method of forming a microphone device includes: forming a through-hole in a substrate wafer; providing a second wafer; bonding the second wafer to the substrate wafer; and forming a top electrode over a first surface of a single-crystal piezoelectric film of the second wafer. The second wafer may include the single-crystal piezoelectric film. The single-crystal piezoelectric film may have a first surface and an opposing second surface. The second wafer may further include a bottom electrode arranged adjacent to the second surface, and a support member over the single-crystal piezoelectric film. The through-hole in substrate wafer may be at least substantially aligned with at least one of the top electrode and the bottom electrode.

公开(公告)号：US10082135B2

公开(公告)日：2018-09-25

申请号：US13508650

申请日：2010-11-12

Applicant: Yves Fouillet ,  Francois Baleras ,  Martine Cochet ,  Sandrine Maubert

Inventor： Yves Fouillet ,  Francois Baleras ,  Martine Cochet ,  Sandrine Maubert

IPC: F04B45/04 ,  F04B43/04 ,  F04B43/02 ,  A61M5/145 ,  B81C1/00

CPC classification number: F04B43/046 ,  A61M5/14586 ,  B81B2201/036 ,  B81B2203/0127 ,  B81C1/00182 ,  B81C2201/0167 ,  B81C2201/019 ,  F04B43/02 ,  F04B43/043 ,  F05C2203/02 ,  F05C2203/06 ,  Y10T29/494

Abstract: A method for producing at least one deformable membrane micropump including a first substrate and a second substrate assembled together, the first substrate including at least one cavity and the second substrate including at least one deformable membrane arranged facing the cavity. In the method: the cavity is produced in the first substrate; then the first and second substrates are assembled together; then the deformable membrane is produced in the second substrate.