公开(公告)号：US5369220A

公开(公告)日：1994-11-29

申请号：US949474

申请日：1992-10-23

Applicant: Keizo Harada ,  Takatoshi Takikawa ,  Takao Maeda ,  Shunsuke Ban ,  Shosaku Yamanaka

Inventor： Keizo Harada ,  Takatoshi Takikawa ,  Takao Maeda ,  Shunsuke Ban ,  Shosaku Yamanaka

IPC: H01L23/14 ,  H01L23/495 ,  H01L23/498 ,  H05K1/05 ,  H01L39/02 ,  H01L23/48 ,  H01L29/46 ,  H01L29/62

CPC classification number: H05K1/053 ,  H01L23/142 ,  H01L23/49517 ,  H01L23/49531 ,  H01L23/49866 ,  H01L24/49 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H05K2201/0179 ,  H05K2201/0317

Abstract: A wiring board has a wiring circuit which is reliable and which can be easily miniaturized, and used for the production of a highly integrated, lighter, thinner, shorter, smaller and low-cost semiconductor device. This wiring board can be sealed in a plastic package. The wiring board has a metal plate and a thin-film dielectric layer formed on the surface of the metal plate. A semiconductor device is mounted on the surface of the dielectric layer or the exposed surface of the metal plate. Film wirings are formed on the dielectric layer. Each film wiring is in the form of a laminate formed by laminating, by vapor phase deposition or by plating, a an aluminum conductive layer, an adhesive layer of chromium, titanium or a laminate thereof, a diffusion barrier layer of nickel, copper or a laminate thereof, and a corrosion-preventive and wire bonding layer of gold. Such wirings may alternatively be in the form of a laminate formed by laminating an adhesive layer of chromium, aluminum, titanium or a laminate comprising at least two of such materials, a copper conductive layer, and a gold layer, or in the form of a laminate formed by laminating an aluminum conductive layer, a barrier layer of nickel, and a gold layer. Since the film wirings can be miniaturized easily, the density of the wirings can be increased. Also, since the wirings are made of aluminum or copper, they are inexpensive.

Abstract translation: PCT No.PCT / JP92 / 00198 Sec。 371日期：1992年10月23日 102（e）日期1992年10月23日PCT提交1992年2月24日PCT公布。 公开号WO92 / 15117 日期：1992年9月3日。线路板具有可靠的并且可以容易地小型化的布线电路，并且用于生产高度集成，更轻，更薄，更短，更小和更低成本的半导体器件。 该接线板可以用塑料封装密封。 布线板具有形成在金属板表面上的金属板和薄膜电介质层。 半导体器件安装在电介质层的表面或金属板的暴露表面上。 在电介质层上形成膜布线。 每个薄膜布线是通过气相沉积或电镀层压铝，导电层，铬，钛或其层压体的粘合剂层，镍，铜或铜的扩散阻挡层而形成的层压体 层压板，以及金的防腐蚀和引线接合层。 这种布线也可以是通过层压铬，铝，钛或包含这些材料中的至少两种的层压体，铜导电层和金层，或者以 通过层叠铝导电层，镍的阻挡层和金层形成的层压体。 由于薄膜布线可以容易地小型化，所以可以提高布线的密度。 此外，由于布线由铝或铜制成，所以价格便宜。

公开(公告)号：US5328534A

公开(公告)日：1994-07-12

申请号：US21155

申请日：1993-02-22

Applicant: Clyde D. Calhoun ,  David C. Koskenmaki

Inventor： Clyde D. Calhoun ,  David C. Koskenmaki

IPC: B41M5/00 ,  B05D5/06 ,  B41M1/22 ,  B44C1/14 ,  B44C1/165 ,  B44C3/08 ,  H05K3/04 ,  H05K3/20 ,  H05K3/38 ,  B29C41/02

CPC classification number: B44C3/08 ,  B41M1/22 ,  B44C1/14 ,  H05K3/046 ,  H05K3/20 ,  H05K2201/0317 ,  H05K3/386 ,  Y10T156/1023 ,  Y10T156/1039 ,  Y10T156/1041

Abstract: A method of forming a transferable pattern or image of an inorganic film by coating an embossed substrate with an inorganic layer, that may comprise one or more films, over both recessed and raised surface portions, adhesively laminating a transfer substrate to the inorganic layer coating the raised surface portions of the embossed substrate and separating the embossed substrate and the transfer substrate. The adhesive is selected such that the bond between the transfer substrate and the inorganic film on the raised surface portions is greater than the bond between the inorganic layer on the raised surface portions and the embossed substrate.The embossed substrate resulting after removal of the inorganic layer coating the raised surface portions may be modified to include additional inorganic layers over the recessed surface portions by tinning or electroplating methods such that this thickened inorganic layer may also be transferred from the embossed substrate to a transfer substrate as set forth above.

Abstract translation: 通过在两个凹凸表面部分上涂覆可以包含一个或多个膜的无机层的压花基材来形成无机膜的可转移图案或图像的方法，将转印基材粘附到无机层上涂布 压花基板的凸起表面部分并分离压花基板和转印基板。 选择粘合剂使得转印衬底和凸起表面部分上的无机膜之间的结合大于凸起表面部分上的无机层与压花衬底之间的结合。 在除去涂覆凸起表面部分的无机层之后产生的压花基材可以通过镀锡或电镀方法改性成在凹面部分上包括额外的无机层，使得该增厚的无机层也可以从压花基底转移到转印 底物如上所述。

公开(公告)号：US5296651A

公开(公告)日：1994-03-22

申请号：US014973

申请日：1993-02-09

Applicant: Francis E. Gurrie ,  Wojtek Sudol

Inventor： Francis E. Gurrie ,  Wojtek Sudol

IPC: H01B7/08 ,  H05K1/02 ,  H05K1/11 ,  H05K3/28 ,  H05K3/38 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K1/0218 ,  H05K1/118 ,  H05K1/0215 ,  H05K2201/0317 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09754 ,  H05K2201/1034 ,  H05K3/281 ,  H05K3/386 ,  H05K3/4614 ,  Y10S428/901

Abstract: A flexible circuit suitable for high density applications and having a long flexural life is disclosed. A thin film metallic ground plane deposited on a dielectric substrate electrically shields the conductor traces in the flexible circuit and eliminates cross-talk between conductor traces without reducing the flexibility or the flexural life of the flexible circuit.

Abstract translation: 公开了一种适用于高密度应用并具有长弯曲寿命的柔性电路。 沉积在电介质基板上的薄膜金属接地面电屏蔽柔性电路中的导体迹线，并消除导体迹线之间的串扰，而不会降低柔性电路的灵活性或弯曲寿命。

公开(公告)号：US5185502A

公开(公告)日：1993-02-09

申请号：US598103

申请日：1990-10-16

Applicant: Lloyd T. Shepherd ,  Melvin C. August ,  James N. Kruchowski

Inventor： Lloyd T. Shepherd ,  Melvin C. August ,  James N. Kruchowski

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H05K1/02 ,  H05K1/16 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/0265 ,  H01L21/4857 ,  H01L23/49866 ,  H01L23/50 ,  H01L23/5383 ,  H05K3/421 ,  H05K3/422 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/167 ,  H05K2201/0317 ,  H05K2201/0376 ,  H05K2201/09309 ,  H05K2203/0315 ,  H05K2203/0361 ,  H05K2203/072 ,  H05K2203/0733 ,  H05K3/388 ,  H05K3/4661 ,  H05K3/467

Abstract: The present invention provides an improved method for manufacturing circuit boards with high power, high density interconnects. Printed circuit board technology, integrated circuit technology, and heavy-build electroless plating are combined to produce multilayer circuit boards comprised of substrates with different interconnect densities. In the higher density substrates, thick metallized layers are built-up by combining additive and subtractive techniques. These thicker foils minimize DC voltage drop so that conductors can run for longer distances. The conductors are substantially more square than their thin film equivalents, thus providing better performance for high frequency signals. Power distribution capabilities are enhanced by the present invention, so that circuit boards fully populated with dense, high-speed, high-power integrated circuits can easily be supplied with their necessary power requirements.

Abstract translation: 本发明提供了一种用于制造具有高功率，高密度互连的电路板的改进方法。 将印刷电路板技术，集成电路技术和重构无电镀技术相结合，生产出具有不同互连密度的基板组成的多层电路板。 在较高密度的衬底中，通过组合加和减法技术来构建厚的金属化层。 这些较厚的箔片最小化直流电压降，以便导体可以运行更长的距离。 导体比它们的薄膜当量大得多的平方，从而为高频信号提供更好的性能。 通过本发明增强了配电能力，使得充分填充密集的高速大功率集成电路的电路板可以容易地提供其所需的功率要求。

公开(公告)号：US5122439A

公开(公告)日：1992-06-16

申请号：US399058

申请日：1989-08-28

Applicant: Ekkehard F. Miersch ,  Jae M. Park

Inventor： Ekkehard F. Miersch ,  Jae M. Park

IPC: G03C1/00 ,  C25F5/00 ,  G03F1/08 ,  H01L21/48 ,  H05K3/04 ,  H05K3/06 ,  H05K3/10 ,  H05K3/16 ,  H05K3/24

CPC classification number: H05K3/045 ,  H01L21/4846 ,  H05K2201/0317 ,  H05K2203/0195 ,  H05K2203/025 ,  H05K2203/0353 ,  H05K3/06 ,  H05K3/107

Abstract: A pattern is formed on a substrate by providing on the substrate a dielectric composition; defining a pattern in said dielectric; depositing metal and then micromachining the metal to provide the desired pattern on the substrate.

公开(公告)号：US5061552A

公开(公告)日：1991-10-29

申请号：US469788

申请日：1990-01-24

Applicant: Kazuaki Satou

Inventor： Kazuaki Satou

IPC: H01L21/60 ,  H01L21/48 ,  H01L23/498 ,  H05K1/03 ,  H05K1/09 ,  H05K3/24 ,  H05K3/34

CPC classification number: H05K3/3452 ,  H01L21/4853 ,  H01L23/49816 ,  H01L2924/00013 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K2201/0317 ,  H05K2201/2081 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A multi-layer ceramic substrate assembly comprising a multi-layer ceramic substrate including a via-conductor and an interconnecting line and having a surface, a first soldering pad on the surface of the substrate and electrically connected to the via-conductor, a second soldering pad on the surface of the substrate adjacent to the first soldering pad, a connecting pattern on the surface of the substrate for electrically connecting the first and second soldering pads, the connecting pattern being made of an electric conductor wettable with a solder, and a solder dam formed on the connecting pattern between the first and second soldering pads, the solder dam being made of a metal or a metal alloy or compound not wettable with a solder. The electric conductivity of the connecting pattern is carried by a metal having a good electric conductivity and the solder dam is made of a metal or a metal alloy or compound not wettable with a solder, whereby the solder dam stops a flow of a solder through the dam or under the dam. A simple and reliable process for forming such a solder dam is also provided.

公开(公告)号：US5051811A

公开(公告)日：1991-09-24

申请号：US302852

申请日：1989-01-27

Applicant: Ralph E. Williams ,  David B. Rhine ,  John Bedinger ,  Larry G. Barnett

Inventor： Ralph E. Williams ,  David B. Rhine ,  John Bedinger ,  Larry G. Barnett

IPC: B23K1/20 ,  B23K35/22 ,  H01L21/60 ,  H05K3/00 ,  H05K3/04 ,  H05K3/34 ,  H05K3/40

CPC classification number: H01L24/83 ,  B23K1/20 ,  B23K35/224 ,  H01L24/32 ,  H05K3/0094 ,  H05K3/40 ,  B23K2201/40 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15787 ,  H05K2201/0317 ,  H05K2201/2081 ,  H05K3/048 ,  H05K3/3452 ,  H05K3/4076

Abstract: A method of preparing a substrate such as a semiconductor chip or ceramic thin film having vias for soldering to a substrate requires that a first metal that is resistive to solder bonding be deposited on the backside of the semiconductor device. The deposited metal is removed from the surface of the semiconductor device, leaving the vias of the semiconductor device having the first metal deposited through them. This technique is useful in any requirement requiring a solder or brazing barrier. This is, a photolithographic process in conjunction with a refractory or nonsolderable metal deposit is used to achieve an alloy or solder barrier.

Abstract translation: 制备诸如具有用于焊接到衬底的通孔的半导体芯片或陶瓷薄膜的衬底的方法需要在半导体器件的背面上沉积耐焊接接合的第一金属。 从半导体器件的表面去除沉积的金属，留下通过它们沉积第一金属的半导体器件的通孔。 这种技术在需要焊料或钎焊屏障的任何要求中都是有用的。 这是与耐火材料或不可焊接的金属沉积物相结合的光刻工艺被用于实现合金或焊料屏障。

公开(公告)号：US5009744A

公开(公告)日：1991-04-23

申请号：US311097

申请日：1989-02-15

Applicant: Harufumi Mandai ,  Yukio Tanaka ,  Shinichi Takakura ,  Takuji Nakagawa

Inventor： Harufumi Mandai ,  Yukio Tanaka ,  Shinichi Takakura ,  Takuji Nakagawa

IPC: H01G4/12 ,  C04B41/51 ,  C04B41/88 ,  H01G4/30 ,  H05K1/03 ,  H05K3/20 ,  H05K3/46

CPC classification number: C04B41/009 ,  C04B41/51 ,  C04B41/88 ,  H01G4/308 ,  H05K3/20 ,  H05K3/4611 ,  H05K3/4629 ,  C04B2111/00612 ,  H05K1/0306 ,  H05K2201/0317 ,  H05K2203/0156 ,  Y10T156/1707 ,  Y10T29/4981

Abstract: A metal film (12) for providing internal electrodes (22) is formed on a back film (11) made of a material such as polyethylene terephthalate by a thin film forming method such as vapor deposition or sputtering. A ceramic green sheet (14) is prepared. Then the metal film (12) is transferred onto the green sheet from the back film (11). In order to form the metal film (12) to be transferred into prescribed patterns, the metal film (12) may be partially removed from the back film (11) to leave only specific parts which are correlative with the prescribed patterns. Alternatively, only specific parts, which are correlative with the prescribed patterns, of the back film (11) may be pressed against the ceramic green sheet (14). A plurality of such ceramic green sheets (14), onto which the parts of the metal films (120 are transferred, have been stacked with each other.

公开(公告)号：US4576659A

公开(公告)日：1986-03-18

申请号：US446300

申请日：1982-12-02

Applicant: Robert K. Lewis ,  Sudipta K. Ray

Inventor： Robert K. Lewis ,  Sudipta K. Ray

IPC: H01L21/60 ,  B23K35/38 ,  C23C26/00 ,  H01L21/48 ,  H05K1/03 ,  H05K1/09 ,  H05K3/22 ,  H05K3/24 ,  H05K3/34 ,  B23K31/02 ,  C21D1/74

CPC classification number: H01L24/05 ,  B23K35/383 ,  C23C26/00 ,  H01L21/4846 ,  H01L24/03 ,  H05K3/22 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K1/0306 ,  H05K1/09 ,  H05K2201/0317 ,  H05K2203/0315 ,  H05K2203/087 ,  H05K2203/1105 ,  H05K2203/1157 ,  H05K3/244 ,  H05K3/341 ,  H05K3/3489 ,  Y10T428/12528 ,  Y10T428/12889 ,  Y10T428/12903

Abstract: The formation of metal oxide contaminants on the surfaces of thin metal films by out-diffusion primarily through the grain boundaries thereof of metal from an underlayer is inhibited by conducting heat cycling of such layered metal structures in an ambient gas mixture composed of inert gas, such as nitrogen, containing a sufficient amount of active gas, such as, hydrogen, carbon monoxide, or the like, substantially to suppress such out-diffusion.

Abstract translation: 金属氧化物污染物在金属薄膜的表面上的形成通过主要通过其从底层的金属的晶粒边界扩散而在金属薄膜的表面上的形成受到这种层状金属结构在由惰性气体组成的环境气体混合物中的热循环的抑制， 作为氮气，含有足够量的活性气体，例如氢气，一氧化碳等，基本上抑制这种扩散。

公开(公告)号：US4568413A

公开(公告)日：1986-02-04

申请号：US582274

申请日：1984-02-22

Applicant: James J. Toth ,  William J. Toth

Inventor： James J. Toth ,  William J. Toth

IPC: B32B38/10 ,  C23C14/00 ,  H05K3/02 ,  C25D5/00 ,  B05D5/12 ,  B32B31/00

CPC classification number: B32B38/10 ,  C23C14/0005 ,  H05K3/025 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2203/0156 ,  H05K2203/0315 ,  H05K2203/0726 ,  Y10T428/12396 ,  Y10T428/31681

Abstract: A carrier (10) is vapor-vacuum deposited with a vapor-vacuum deposited first metallic layer (14) of 10-90 nm in thickness. The carrier and vapor-vacuum deposited metal layers are selected of materials which, after vapor-vacuum depositing, adhere with less than about 3 pounds per linear inch of width, e.g., aluminum and copper or copper and copper. A second metallic layer (16) is electrolytically deposited to the vapor-vacuum deposited layer to increase the thickness of the first and second metal layers, taken together, to about 1-12 microns. The carrier and first and second metal layers are bonded under heat and pressure to a dielectric substrate (18). Thereafter, the carrier is peeled away leaving the vapor-vacuum deposited and electrolytically plated layers adhered to the dielectric substrate. Although the vapor-vacuum deposited layer and the electrolytically deposited layers may both be the same metal, such as copper which is preferred for circuit boards, the vapor-vacuum deposited layer may also be a relatively inactive metal, such as aluminum, chrome, zinc, or nickel, to protect the underlying electrolytically deposited metal layer from corrosion and staining.

Abstract translation: 用厚度为10-90nm的蒸气 - 真空沉积的第一金属层（14）对载体（10）进行气相真空沉积。 载体和蒸气 - 真空沉积的金属层选自在蒸气真空沉积之后以小于约3磅每线性英寸宽度粘附的材料，例如铝和铜或铜和铜。 将第二金属层（16）电解沉积到蒸气 - 真空沉积层，以将第一和第二金属层的厚度一起提高到约1-12微米。 载体和第一和第二金属层在热和压力下结合到电介质基板（18）。 此后，将载体剥离，留下蒸镀真空沉积并电解电镀的层粘附到电介质基片上。 虽然蒸气 - 真空沉积层和电解沉积层可以都是相同的金属，例如优选用于电路板的铜，但蒸气真空沉积层也可以是相对不活泼的金属，例如铝，铬，锌 或镍，以保护底层的电解沉积金属层免受腐蚀和污染。