公开(公告)号：US09699908B2

公开(公告)日：2017-07-04

申请号：US14627194

申请日：2015-02-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takahiro Baba ,  Yuki Wakabayashi

IPC: H05K1/18 ,  H01L23/00 ,  H05K3/46 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/183 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1531 ,  H01L2924/19105 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/0326 ,  H05K1/181 ,  H05K1/186 ,  H05K3/4617 ,  H05K2201/0141 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2203/0278 ,  H05K2203/063 ,  H01L2924/00

Abstract: A component-embedded board includes a multilayer board obtained by stacking resin layers and an electronic component in the multilayer board having terminal electrodes on at least one principal face. The resin layers include a first resin layer having a space to accommodate the electronic component and at least one first interlayer connector formed by solidifying a conductive paste outside each of at least three sides of a principal face of the electronic component and a second resin layer having second and third interlayer connectors formed by solidifying a conductive paste. At least one second interlayer connector is positioned outside the three sides of the principal face. The third interlayer connectors are joined to the terminal electrodes. The first resin layer and the second resin layer are adjacent to each other in a stacking direction within the multilayer board. The first interlayer connector and the second interlayer connector are joined.

公开(公告)号：US20170019993A1

公开(公告)日：2017-01-19

申请号：US14798384

申请日：2015-07-13

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  H05K3/00 ,  H05K3/22 ,  H05K1/02 ,  H05K3/36

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor module and a method for manufacturing the same. The semiconductor substrate includes a first dielectric structure, a second dielectric structure, a first patterned conductive layer and a second patterned conductive layer. The first dielectric structure has a first surface and a second surface opposite the first surface. The second dielectric structure has a third surface and a fourth surface opposite the third surface, where the fourth surface is adjacent to the first surface. The second dielectric structure defines a through hole extending from the third surface to the fourth surface. A cavity is defined by the through hole and the first dielectric structure. The first patterned conductive layer is disposed on the first surface of the first dielectric structure. The second patterned conductive layer is disposed on the second surface of the first dielectric structure.

Abstract translation: 本公开涉及半导体衬底，半导体模块及其制造方法。 半导体衬底包括第一电介质结构，第二电介质结构，第一图案化导电层和第二图案化导电层。 第一电介质结构具有与第一表面相对的第一表面和第二表面。 第二电介质结构具有与第三表面相对的第三表面和第四表面，其中第四表面与第一表面相邻。 第二电介质结构限定了从第三表面延伸到第四表面的通孔。 空腔由通孔和第一电介质结构限定。 第一图案化导电层设置在第一电介质结构的第一表面上。 第二图案化导电层设置在第一介电结构的第二表面上。

公开(公告)号：US20160353585A1

公开(公告)日：2016-12-01

申请号：US15236794

申请日：2016-08-15

Applicant: Marvell World Trade Ltd.

Inventor： Huahung Kao ,  Shiann-Ming Liou

IPC: H05K3/46 ,  H05K3/10 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K3/4611 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/0026 ,  H05K3/0035 ,  H05K3/10 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/4655 ,  H05K2201/09518 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2203/107 ,  Y10T156/1057 ,  H01L2924/00

Abstract: Embodiments include a multi-layer apparatus comprising a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer, wherein one or more of the dielectric layers include metal layers. The multi-layer apparatus further comprises a first via coupling a first metal layer and a second metal layer, a second via coupling the second metal layer and a fourth metal layer, a third via coupling the first metal layer and the second metal layer, and a fourth via coupling the third metal layer and the fourth metal layer. The first via is contiguous with the second via and the third via is contiguous with the fourth via. At least some of the vias have different depths relative to one another.

公开(公告)号：US09320153B2

公开(公告)日：2016-04-19

申请号：US14548725

申请日：2014-11-20

Applicant: IBIDEN CO., LTD.

Inventor： Masahiro Kaneko ,  Satoru Kose ,  Hirokazu Higashi

IPC: H05K3/02 ,  H05K3/10 ,  H05K3/42 ,  H01L21/683 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H05K1/11 ,  H05K1/03 ,  H05K3/22 ,  H05K3/00 ,  H05K3/38

CPC classification number: H05K3/42 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85001 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0313 ,  H05K1/113 ,  H05K1/115 ,  H05K3/007 ,  H05K3/108 ,  H05K3/22 ,  H05K3/388 ,  H05K2201/0344 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/1377 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed wiring board includes an interlayer resin insulation layer having a penetrating hole, a conductive circuit formed on a first surface of the interlayer resin insulation layer, a filled via conductor formed in the penetrating hole of the interlayer resin insulation layer and connected to the conductive circuit, a first surface-treatment coating structure formed on a first surface of the filled via conductor and having an electroless plating structure, and a second surface-treatment coating structure formed on a second surface of the filled via conductor on an opposite side with respect to the first surface-treatment coating structure and having an electroless plating structure. The filled via conductor includes a first conductive layer formed on side wall of the penetrating hole and a plated material filling the penetrating hole, and the first surface-treatment coating structure has a thickness which is different from a thickness of the second surface-treatment coating structure.

Abstract translation: 印刷电路板包括具有贯通孔的层间树脂绝缘层，形成在层间树脂绝缘层的第一表面上的导电电路，形成在层间树脂绝缘层的穿透孔中并与导电 电路，形成在填充的通路导体的第一表面上并具有无电解电镀结构的第一表面处理涂层结构和形成在填充通孔导体的第二表面上的第二表面处理涂层结构，该第二表面处理涂层结构相对于 涉及第一表面处理涂层结构并具有化学镀层结构。 填充的通孔导体包括形成在穿透孔的侧壁上的第一导电层和填充穿透孔的电镀材料，第一表面处理涂层结构的厚度与第二表面处理涂层的厚度不同 结构体。

公开(公告)号：US20150319866A1

公开(公告)日：2015-11-05

申请号：US14794956

申请日：2015-07-09

Applicant: IBIDEN CO., LTD.

Inventor： Yoshinori TAKENAKA

IPC: H05K3/30 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/30 ,  H05K1/0233 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09527 ,  H05K2201/09672 ,  Y10T29/49021 ,  Y10T29/4913

Abstract: A wiring board includes a core structure having a first surface and a second surface on the opposite side of the first surface, a first buildup structure formed on the first surface of the core structure and including insulation layers, and a second buildup structure formed on the second surface of the core structure and including insulation layers and an inductor device. The insulation layers in the second buildup structure have the thicknesses which are thinner than the thicknesses of the insulation layers in the first buildup structure, and the inductor device in the second buildup structure is position on the second surface of the core structure and includes at least a portion of a conductive pattern formed in the core structure.

Abstract translation: 布线基板包括具有在第一表面的相对侧的第一表面和第二表面的芯结构，形成在芯结构的第一表面上并且包括绝缘层的第一堆积结构，以及形成在第一堆积结构上的第二堆积结构 芯结构的第二表面并包括绝缘层和电感器件。 第二堆积结构中的绝缘层具有比第一堆积结构中的绝缘层的厚度薄的厚度，并且第二堆叠结构中的电感器件位于芯结构的第二表面上并且至少包括 形成在芯结构中的导电图案的一部分。

公开(公告)号：US09153541B2

公开(公告)日：2015-10-06

申请号：US12032444

申请日：2008-02-15

Applicant: Junji Tanaka

Inventor： Junji Tanaka

IPC: H01L23/02 ,  H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/12 ,  H01L23/053 ,  H01L29/40 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/18 ,  H01L25/03 ,  H05K1/11 ,  H05K3/20 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/113 ,  H05K1/187 ,  H05K3/20 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2203/049 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a first insulator film having a first opening, a first wiring layer extending from the first opening onto the first insulator film, a first semiconductor chip mounted on the first insulator film so as to be electrically coupled with the first wiring layer, and a resin portion applied on the first insulation film to cover the first semiconductor chip.

Abstract translation: 半导体器件包括具有第一开口的第一绝缘膜，从第一开口延伸到第一绝缘膜上的第一布线层，安装在第一绝缘膜上以与第一布线层电耦合的第一半导体芯片， 以及施加在第一绝缘膜上以覆盖第一半导体芯片的树脂部分。

公开(公告)号：US20150257281A1

公开(公告)日：2015-09-10

申请号：US14642098

申请日：2015-03-09

Applicant: Marvell World Trade Ltd.

Inventor： Huahung Kao ,  Shiann-Ming Liou

IPC: H05K3/40 ,  H05K1/11 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K3/4611 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/0026 ,  H05K3/0035 ,  H05K3/10 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/4655 ,  H05K2201/09518 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2203/107 ,  Y10T156/1057 ,  H01L2924/00

Abstract: Embodiments include a multi-layer apparatus comprising a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer, wherein one or more of the dielectric layers include metal layers. The multi-layer apparatus further comprises a first via coupling a first metal layer and a second metal layer, a second via coupling the second metal layer and a fourth metal layer, a third via coupling the first metal layer and the second metal layer, and a fourth via coupling the third metal layer and the fourth metal layer. The first via is contiguous with the second via and the third via is contiguous with the fourth via. At least some of the vias have different depths relative to one another.

Abstract translation: 实施例包括包括第一电介质层，第二电介质层，第三电介质层和第四电介质层的多层设备，其中一个或多个电介质层包括金属层。 多层设备还包括第一通孔耦合第一金属层和第二金属层，耦合第二金属层和第四金属层的第二通孔，耦合第一金属层和第二金属层的第三通孔，以及 第四通孔，其耦合所述第三金属层和所述第四金属层。 第一通孔与第二通孔相邻，第三通孔与第四通孔相邻。 至少一些通孔相对于彼此具有不同的深度。

公开(公告)号：US20150008020A1

公开(公告)日：2015-01-08

申请号：US14310076

申请日：2014-06-20

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kentaro KANEKO ,  Katsuya FUKASE

IPC: H05K1/11 ,  H05K1/09 ,  H05K1/02

CPC classification number: H05K3/465 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/4679 ,  H05K2201/09527 ,  H05K2203/025

Abstract: A wiring board includes a first wiring layer including a first conductive layer and a second conductive layer coating a first surface and a side surface of the first conductive layer. A first insulating layer covers a first surface and a side surface of the second conductive layer so as to expose a second surface of the first conductive layer opposite to the first surface of the first conductive layer. A second wiring layer is stacked on a first surface of the first insulating layer and is electrically connected to the first wiring layer. The first surface and the side surface of the first conductive layer are smooth surfaces while the first surface and the side surface of the second conductive layer are roughened-surfaces.

Abstract translation: 布线基板包括第一布线层，第一布线层包括第一导电层和涂覆第一导电层的第一表面和侧表面的第二导电层。 第一绝缘层覆盖第二导电层的第一表面和侧表面，以暴露与第一导电层的第一表面相对的第一导电层的第二表面。 第二布线层堆叠在第一绝缘层的第一表面上并与第一布线层电连接。 第一导电层的第一表面和侧表面是平滑表面，而第二导电层的第一表面和侧表面是粗糙表面。

公开(公告)号：US20140034365A1

公开(公告)日：2014-02-06

申请号：US14047623

申请日：2013-10-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshihito OTSUBO

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K1/028 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/09 ,  H05K2201/09527 ,  H05K2201/096 ,  Y10T29/49165 ,  Y10T428/1259 ,  Y10T428/24355 ,  Y10T428/31663

Abstract: A flexible multilayer substrate includes a multilayer body including a plurality of laminated resin layers. The multilayer body includes an innermost surface, which is a surface on an inner side when the substrate is bent, and an outermost surface, which is a surface on an outer side when the substrate is bent. Each of the plurality of resin layers includes a skin layer on one surface. Lamination of the multilayer body includes a skin layer joint plane at one location at a central portion in the thickness direction, and the skin layer and other surface come in contact with each other at another location along the central portion in the thickness direction. A skin layer joint plane is arranged on a side closer to the innermost surface than a central plane in the thickness direction of the multilayer body.

Abstract translation: 柔性多层基板包括具有多个层叠树脂层的多层体。 所述多层体包含最内表面，所述最内表面是当所述基材弯曲时在内侧的表面，以及最外表面，所述最外表面是当所述基材弯曲时在外侧的表面。 多个树脂层中的每一个在一个表面上包括表皮层。 多层体的层叠包括在厚度方向的中央部的一个位置处的表皮层接合面，并且表皮层和其他表面在厚度方向上沿着中心部分的另一位置彼此接触。 表皮层接合面布置在比多层体的厚度方向上的中心平面更靠近最内表面的一侧。

公开(公告)号：US08624121B2

公开(公告)日：2014-01-07

申请号：US13114693

申请日：2011-05-24

Applicant: Ayao Niki

Inventor： Ayao Niki

IPC: H05K1/00

CPC classification number: H05K1/115 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0554 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49162

Abstract: A multilayer printed wiring board includes one or more resin layers having via-holes and a core layer having via-holes. The via-holes formed in the one or more resin layers are open in the direction opposite to the direction in which the via-holes formed in the core layer are open. A method for manufacturing a multilayer printed wiring board includes a step of preparing a single- or double-sided copper-clad laminate; a step of forming lands by processing the copper-clad laminate; a step of forming a resin layer on the upper surface of the copper-clad laminate, forming openings for via-holes in the resin layer, and then forming the via-holes; and a step of forming openings for via-holes in the lower surface of the copper-clad laminate and then forming the via-holes.

Abstract translation: 多层印刷线路板包括一个或多个具有通孔的树脂层和具有通孔的芯层。 在一个或多个树脂层中形成的通孔在与芯层中形成的通路孔打开的方向相反的方向上开口。 一种制造多层印刷线路板的方法包括制备单面或双面覆铜层压板的步骤; 通过加工覆铜层压板来形成焊盘的步骤; 在覆铜层压板的上表面上形成树脂层的步骤，在树脂层中形成通孔的开口，然后形成通孔; 以及在覆铜层压板的下表面中形成用于通孔的开口，然后形成通孔的步骤。