公开(公告)号：US11706878B2

公开(公告)日：2023-07-18

申请号：US17351664

申请日：2021-06-18

Applicant: INNOGRIT TECHNOLOGIES CO., LTD.

Inventor： Yanwen Bai ,  Shiann-Ming Liou ,  Gang Zhao ,  Lin Chen

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/16 ,  H05K3/40 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46 ,  H01L23/15 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H05K3/00

CPC classification number: H05K3/4688 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/0094 ,  H05K2201/0959 ,  H05K2201/09518

Abstract: The present disclosure discloses a multilayer circuit board comprising a plurality of metal layers, a blind via and/or a buried via, the multilayer circuit board is capable of transmitting signal between the different metal layers. The blind via has a pad on a non-opening side of the blind via. An upper or lower layer metal layer on the non-opening side of the blind via adjacent to the blind via has a first hole which is located in a position corresponding to the pad on the non-opening side of the blind via in a depth direction of the blind via; and/or an upper and/or lower layer adjacent to the buried via has a second hole which is located in a position corresponding to the pad of an upper and/or lower orifice of the buried via in a depth direction of the buried via.

公开(公告)号：US20170118844A1

公开(公告)日：2017-04-27

申请号：US15175378

申请日：2016-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce J. CHAMBERLIN ,  Andreas HUBER ,  Harald HUELS ,  Thomas STRACH ,  Thomas-Michael WINKEL

IPC: H05K3/34 ,  H05K3/40 ,  B23K1/00 ,  H05K3/00 ,  B23K1/20 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K1/184 ,  B23K1/0016 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/111 ,  H05K1/113 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/185 ,  H05K1/186 ,  H05K3/0047 ,  H05K3/3447 ,  H05K3/429 ,  H05K3/46 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09345 ,  H05K2201/09381 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/1006 ,  H05K2201/10174

Abstract: Embedding a discrete electrical device in a printed circuit board (PCB) includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to an electrically conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first electrical device contact device and the electrically conductive structure in the first layer; and establishing a second electrical connection between a second electrical device contact and a second layer, the second layer being one of the electrically conductive layers of a second horizontal core section.

公开(公告)号：US09534751B2

公开(公告)日：2017-01-03

申请号：US14704279

申请日：2015-05-05

Applicant: Mag Instrument, Inc.

Inventor： Anthony Maglica ,  Stacey H. West ,  Robert P. Radloff

IPC: F21L4/02 ,  F21K99/00 ,  F21V15/04 ,  F21V23/04 ,  F21V29/00 ,  F21V23/00 ,  F21V29/507 ,  F21V29/74 ,  F21V29/89 ,  F21V29/508 ,  F21V29/70 ,  H05K1/02 ,  H05K3/42 ,  F21W101/10 ,  F21W111/10 ,  F21Y101/00

CPC classification number: F21V29/70 ,  F21K9/00 ,  F21L4/027 ,  F21V15/04 ,  F21V19/005 ,  F21V23/005 ,  F21V23/006 ,  F21V23/04 ,  F21V23/0414 ,  F21V23/06 ,  F21V29/507 ,  F21V29/508 ,  F21V29/74 ,  F21V29/89 ,  F21W2102/00 ,  F21W2111/10 ,  F21Y2101/00 ,  F21Y2115/10 ,  H05K1/0206 ,  H05K1/0207 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/10106

Abstract: A light emitting diode (“LED”) module with improved thermal characteristics is provided. The module includes an LED, a first circuit board, a second circuit board, a lower insulator, an upper insulator, a lower contact, upper contacts, and a heat sink. Preferably, the heat sink comprises an outer housing and a contact ring. The LED and the heat sink are attached to the first circuit board via solder. In addition to serving as a substrate for the LED, the first circuit board (which contains a plurality of thermally conductive layers connected by vias) facilitates the transfer of heat away from the LED to the heat sink. The module also has improved mechanical and electrical properties, including redundant electrical connections, stable mechanical connections, and a shock-absorbing lower contact. The lower insulator can also be configured to prevent misalignment of the power source with the lower contact when the module is used in a flashlight or other lighting device.

Abstract translation: 提供了具有改善的热特性的发光二极管（“LED”）模块。 该模块包括LED，第一电路板，第二电路板，下绝缘体，上绝缘体，下触点，上触点和散热器。 优选地，散热器包括外壳和接触环。 LED和散热器通过焊料连接到第一个电路板。 除了用作LED的基板之外，第一电路板（其包含通过通孔连接的多个导热层）有助于将热量从LED传递到散热器。 该模块还具有改进的机械和电气性能，包括冗余电气连接，稳定的机械连接和减震触点的较低触点。 下绝缘体还可以被配置为当模块用于手电筒或其他照明装置时，防止电源与下接触件的对准。

公开(公告)号：US09204537B2

公开(公告)日：2015-12-01

申请号：US13623615

申请日：2012-09-20

Applicant: FINISAR CORPORATION

Inventor： Henry Meyer Daghighian ,  Steve Bird ,  Bruce Sramek

IPC: H05K1/02 ,  H04B10/40 ,  H01P3/08 ,  H05K3/46 ,  H05K1/03 ,  H05K1/16 ,  H05K3/40 ,  H05K3/42

CPC classification number: H05K1/0283 ,  H01P3/08 ,  H01P3/088 ,  H04B10/40 ,  H05K1/0242 ,  H05K1/0251 ,  H05K1/0373 ,  H05K1/0393 ,  H05K1/16 ,  H05K1/165 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/4691 ,  H05K2201/0141 ,  H05K2201/015 ,  H05K2201/086 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/10121 ,  H05K2201/10189 ,  H05K2201/2009

Abstract: High-speed pluggable rigid-end flex circuit. A circuit includes a flexible section, rigid section, connector disposed on the rigid section, and electrically conductive signal transmission line electrically coupled to the connector. The flexible section includes a first portion of a flexible insulating layer. The rigid section includes a second portion of the flexible insulating layer and a rigid insulating layer disposed on the second portion of the flexible insulating layer. The connector is configured to form a pluggable conductive connection. The electrically conductive signal transmission line includes a first signal trace having a root mean square surface roughness below 20 micrometers and a filled signal via configured to pass through at least a portion of the rigid insulating layer. The flexible and rigid insulating layers have a dissipation factor equal to or below a ratio of 0.004 and a dielectric constant equal to or below a ratio of 3.7.

Abstract translation: 高速可插拔刚性端柔性电路。 电路包括柔性部分，刚性部分，设置在刚性部分上的连接器，以及电连接到连接器的导电信号传输线。 柔性部分包括柔性绝缘层的第一部分。 刚性部分包括柔性绝缘层的第二部分和设置在柔性绝缘层的第二部分上的刚性绝缘层。 连接器被配置成形成可插拔的导电连接。 导电信号传输线包括具有低于20微米的均方根粗糙度的第一信号迹线和经配置以穿过刚性绝缘层的至少一部分的填充信号通道。 柔性和刚性绝缘层的损耗因子等于或低于0.004的比例和等于或低于3.7的介电常数。

公开(公告)号：US20150327363A1

公开(公告)日：2015-11-12

申请号：US14706269

申请日：2015-05-07

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi INAGAKI ,  Yasuhiro Takahashi ,  Satoshi Kurokawa

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/18 ,  H05K1/03 ,  H05K1/11

CPC classification number: H05K1/0243 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L25/18 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/112 ,  H05K1/115 ,  H05K1/181 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4644 ,  H05K2201/0949 ,  H05K2201/09518 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A package substrate includes an inner interlayer, a first conductor layer, a second conductor layer, an outermost interlayer, an outermost conductor layer including first and second pads to mount electronic components, vias including first and second vias such that the first vias are connecting the first conductor layer and first pads and the second vias are connecting the first conductor layer and second pads, and skip vias penetrating through the outermost and inner interlayers such that the skip vias are connecting the outermost and second conductor layers. Sum of insulation distances (t1, t2) is in range of 40 μm or less to 10 μm or more, where the insulation distance (t1) is insulation distance between the outermost and first conductor layers and the insulation distance (t2) is insulation distance between the first and second conductor layers, and difference between the insulation distances (t1, t2) is less than 5 μm.

Abstract translation: 封装基板包括内层，第一导体层，第二导体层，最外层间，最外层导体层，包括用于安装电子元件的第一和第二焊盘，通孔包括第一和第二通孔，使得第一通孔连接 第一导体层和第一焊盘和第二通孔连接第一导体层和第二焊盘，并且跳过穿过最外层和内层的通孔，使得跳过通孔连接最外层导体层和第二导体层。 绝缘距离（t1，t2）之和在绝缘距离（t1）为最外层与第一导体层之间的绝缘距离与绝缘距离（t2）的绝缘距离（t2）为40μm以下至10μm以上的范围内， 在第一和第二导体层之间，绝缘距离（t1，t2）之间的差小于5μm。

公开(公告)号：US20150303074A1

公开(公告)日：2015-10-22

申请号：US14789998

申请日：2015-07-02

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung ,  Wen-Yuan Chang

IPC: H01L21/48 ,  H05K3/42 ,  H01L21/683

CPC classification number: H01L21/4857 ,  H01L21/32 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/48 ,  H01L23/49822 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16238 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2224/81423 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81449 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81469 ,  H01L2224/8148 ,  H01L2924/12042 ,  H01L2924/381 ,  H05K1/113 ,  H05K3/243 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/429 ,  H05K3/4682 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/016 ,  H05K2203/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A process for fabricating a circuit substrate is provided. The process includes the following steps. A carrier is provided. A conductive layer and a dielectric layer are placed on the carrier, and the conductive layer is located between the carrier and the dielectric layer. The dielectric layer is patterned to form a patterned-dielectric layer having first openings partially exposing the conductive layer. Arc-shaped grooves are formed on the exposed part of the conductive layer. A first-patterned-photoresist layer having second openings respectively connecting the first openings is formed. Conductive structures are formed, wherein each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part; the second openings, the first openings and the arc-shaped grooves are respectively filled with the pad parts, the connection parts and the protruding parts. The first patterned photoresist layer, the carrier and the conductive layer are removed.

Abstract translation: 提供了一种用于制造电路基板的工艺。 该过程包括以下步骤。 提供载体。 导电层和电介质层被放置在载体上，并且导电层位于载体和电介质层之间。 图案化电介质层以形成具有部分暴露导电层的第一开口的图案化电介质层。 在导电层的暴露部分上形成弧形槽。 形成具有分别连接第一开口的第二开口的第一图案化光致抗蚀剂层。 形成导电结构，其中每个导电结构一体地形成，并且包括衬垫部分，连接部分和突出部分; 第二开口，第一开口和弧形槽分别填充有垫部分，连接部分和突出部分。 去除第一图案化光致抗蚀剂层，载体和导电层。

公开(公告)号：US09136624B1

公开(公告)日：2015-09-15

申请号：US13852183

申请日：2013-03-28

Applicant: Juniper Networks, Inc.

Inventor： Boris Reynov ,  Venkata S. Raju Penmetsa ,  Ben T. Nitzan ,  Jack W. Kohn ,  Oscar Diaz-Landa ,  Shreeram Siddhaye

IPC: H01R12/00 ,  H01R12/72 ,  H01R43/20 ,  H01R12/50

CPC classification number: H01R23/722 ,  H01R12/7082 ,  H01R12/724 ,  H01R12/737 ,  H05K1/181 ,  H05K3/308 ,  H05K3/366 ,  H05K3/429 ,  H05K7/1444 ,  H05K7/1445 ,  H05K2201/09518 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2201/10492 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/1059

Abstract: A line card of a set of line cards is configured to be coupled to a set of switch-fabric cards to collectively define at least a portion of an orthogonal cross fabric without a midplane board. The line card has an edge portion, a first side and a second side, opposite the first side. The line card includes a set of first set of connectors and a second set of connectors. The first set of connectors is disposed along the edge portion on the first side of the line card and the second set of connectors is disposed along the edge portion on the second side of the line card.

Abstract translation: 一组线路卡的线路卡被配置为耦合到一组交换网卡，以共同限定正交交叉结构的至少一部分而没有中间板。 线卡具有与第一侧相对的边缘部分，第一侧和第二侧。 线卡包括一组第一组连接器和第二组连接器。 第一组连接器沿着线卡的第一侧上的边缘部分布置，并且第二组连接器沿着线卡的第二侧的边缘部分设置。

公开(公告)号：US09098646B2

公开(公告)日：2015-08-04

申请号：US11837181

申请日：2007-08-10

Applicant: Mumtaz Y. Bora ,  Ronald T. Mora

Inventor： Mumtaz Y. Bora ,  Ronald T. Mora

IPC: H05K1/11 ,  G06F17/50 ,  H05K3/00 ,  H05K3/46

CPC classification number: G06F17/50 ,  H05K1/115 ,  H05K3/0005 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/096

Abstract: A printed circuit board (PCB) design system and method allows for PCB layouts that can be manufactured using a PCB manufacturing technology selected from multiple PCB manufacturing technologies with minimal or no modification to the PCB layout. In accordance with the exemplary embodiment, the PCB layout is designed to meet all design rules of a High Density Interconnect (HDI) manufacturing technology while minimizing requirements for layout changes when the PCB is manufactured using an Interstitial Via Hole (IVH) manufacturing technology. An IVH PCB includes a plurality of vias positioned within reserved via areas that form connections between at least some conductive elements on the board layers. The conductive elements and the plurality of vias form a layout such that a majority of reserved via areas, of all of the reserved via areas on the printed circuit board, are adequate to accommodate mechanically drilled vias manufactured with the HDI manufacturing technology.

Abstract translation: 印刷电路板（PCB）设计系统和方法允许使用从多个PCB制造技术中选择的PCB制造技术制造的PCB布局，对PCB布局进行最小化或不改变。 根据示例性实施例，PCB布局被设计成满足高密度互连（HDI）制造技术的所有设计规则，同时在使用间隙通孔（IVH）制造技术制造PCB时最小化对布局变化的要求。 IVH PCB包括多个通孔，其定位在保留的通孔区域内，所述通孔区域在板层上的至少一些导电元件之间形成连接。 导电元件和多个通孔形成布局，使得印刷电路板上的所有预留通孔区域中的大部分预留通孔区域足以容纳用HDI制造技术制造的机械钻孔。

公开(公告)号：US20140374150A1

公开(公告)日：2014-12-25

申请号：US14310354

申请日：2014-06-20

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi INAGAKI ,  Yasuhiro Takahashi ,  Satoshi Kurokawa

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K1/113 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09227 ,  H05K2201/09518 ,  H01L2924/00

Abstract: A package substrate includes an outermost interlayer resin insulation layer, an outermost conductive layer formed on a first surface of the outermost interlayer resin insulation layer and including first pads positioned to mount a first electronic component and second pads positioned to mount a second electronic component, a first conductive layer including first conductive circuits and formed on a second surface of the outermost interlayer resin insulation layer on the opposite side with respect to the first surface, first via conductors penetrating through the outermost interlayer resin insulation layer such that the first via conductors are connecting the first conductive layer and the first pads, and second via conductors penetrating through the outermost interlayer resin insulation layer such that the second via conductors are connecting the first conductive layer and the second pads. The first conductive circuits in the first conductive layer are connecting the first and second pads, respectively.

Abstract translation: 封装衬底包括最外层间树脂绝缘层，最外层导电层，其形成在最外层间树脂绝缘层的第一表面上，并且包括定位成安装第一电子部件的第一焊盘和定位成安装第二电子部件的第二焊盘; 第一导电层包括第一导电电路，并且相对于第一表面在相对侧的最外层间树脂绝缘层的第二表面上形成，第一通孔导体穿过最外层间树脂绝缘层，使得第一通孔导体连接 所述第一导电层和所述第一焊盘，以及穿过所述最外层间树脂绝缘层的第二通孔导体，使得所述第二通孔导体连接所述第一导电层和所述第二焊盘。 第一导电层中的第一导电电路分别连接第一和第二焊盘。

公开(公告)号：US08598468B2

公开(公告)日：2013-12-03

申请号：US13437254

申请日：2012-04-02

Applicant: Han Kim ,  Mi-Ja Han ,  Hyo-Jic Jung

Inventor： Han Kim ,  Mi-Ja Han ,  Hyo-Jic Jung

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H01P1/2005 ,  H01L2224/16 ,  H01P1/203 ,  H05K1/0236 ,  H05K1/0237 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09663 ,  H05K2201/09681

Abstract: An electromagnetic bandgap structure including: at least three conductive plates; a first stitching via, configured to electrically connect any one of the conductive plates to another conductive plate; and a second stitching via, configured to electrically connect the one conductive plate to yet another conductive plate, wherein the first stitching via electrically connects the one conductive plate to another conductive plate by allowing a part of the first stitching via to be connected through a planar surface above or below the one conductive plate, and the second stitching via electrically connects the one conductive plate to yet another conductive plate by allowing a part of the second stitching via to be connected through a planar surface that is different from the planar surface through which the part of the first stitching via is connected, the two planar surfaces being placed in a same direction based on the conductive plates.

Abstract translation: 一种电磁带隙结构，包括：至少三个导电板; 第一缝合通孔，被配置为将任一导电板电连接到另一个导电板; 以及第二缝合通孔，其被配置为将所述一个导电板电连接到另一个导电板，其中所述第一缝合通孔将所述第一缝合通孔的一部分通过平面 表面在一个导电板的上方或下方，并且第二缝合通孔通过允许第二缝合通孔的一部分通过不同于平面的平面表面连接一个导电板到另一个导电板，通过该平面 第一缝合通孔的部分被连接，两个平面被放置在相同的方向上，基于导电板。