公开(公告)号：US20150366063A1

公开(公告)日：2015-12-17

申请号：US14832201

申请日：2015-08-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoichi TAKAGI ,  Tadashi NOMURA ,  Masato YOSHIDA ,  Nobuaki OGAWA ,  Mitsuhiro MATSUMOTO

IPC: H05K1/14 ,  H05K3/34 ,  H05K1/09 ,  H05K3/28

CPC classification number: H05K1/145 ,  H01L23/49811 ,  H01L23/5385 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2924/19105 ,  H05K1/09 ,  H05K1/141 ,  H05K3/284 ,  H05K3/341 ,  H05K2201/0326 ,  H05K2201/09781 ,  H05K2201/10522 ,  H05K2201/10636 ,  H05K2203/1476 ,  Y02P70/611 ,  Y10T29/4913

Abstract: To provide a compact module that is capable of achieving a low profile and that has excellent high-frequency characteristics, a module includes a parent board; first and second child boards arranged so as to face the parent board; multiple electronic components that include first electrodes and second electrodes electrically connected to the first electrodes, respectively, on both opposing faces, the first electrodes being connected to the first child board, the second electrodes being connected to the parent board; and multiple electronic components that include first electrodes and second electrodes electrically connected to the first electrodes, respectively, on both opposing faces, the first electrodes being connected to the second child board, the second electrodes being connected to the parent board.

Abstract translation: 为了提供能够实现低轮廓并且具有优异的高频特性的紧凑模块，模块包括母板; 排列第一和第二个子板，以面对母板; 多个电子部件包括分别在两个相对面上电连接到第一电极的第一电极和第二电极，第一电极连接到第一子板，第二电极连接到母板; 以及多个电子部件，其包括分别在两个相对面上电连接到第一电极的第一电极和第二电极，第一电极连接到第二子板，第二电极连接到母板。

公开(公告)号：US20150364392A1

公开(公告)日：2015-12-17

申请号：US14833341

申请日：2015-08-24

Applicant: Renesas Electronics Corporation

Inventor： Satoshi TAKAHASHI ,  Shuuichi KARIYAZAKI

IPC: H01L23/04 ,  H01L23/367 ,  H01L25/16 ,  H01L23/498

CPC classification number: H01L23/04 ,  H01L21/50 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/544 ,  H01L23/562 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/74 ,  H01L24/97 ,  H01L25/165 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0913 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0266 ,  H05K3/3442 ,  H05K3/3489 ,  H05K2201/066 ,  H05K2201/09781 ,  H05K2201/1056 ,  H05K2201/10636 ,  H05K2203/0169 ,  H05K2203/0173 ,  H05K2203/167 ,  H05K2203/168 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014

Abstract: An error is prevented from being generated at a mounting position of an electronic component on a wiring substrate. A first semiconductor chip has a main surface and a rear surface. The rear surface is an opposite surface of the main surface. The rear surface of the first semiconductor chip is an opposite surface of the main surface thereof. A wiring substrate is rectangular, and has a main surface and a rear surface. The first semiconductor chip is mounted on the main surface of the wiring substrate. A lid covers the main surface of the wiring substrate, and the first semiconductor chip. An electronic component is mounted on the rear surface of the wiring substrate. The main surface of the wiring substrate has uncovered regions that are not covered with the lid at at least two corners facing each other.

Abstract translation: 防止在布线基板上的电子部件的安装位置产生误差。 第一半导体芯片具有主表面和后表面。 后表面是主表面的相反表面。 第一半导体芯片的后表面是其主表面的相对表面。 布线基板是矩形的，并且具有主表面和后表面。 第一半导体芯片安装在布线基板的主表面上。 盖子覆盖布线基板的主表面和第一半导体芯片。 电子部件安装在布线基板的背面。 布线基板的主表面在至少两个彼此面对的角部处未被盖子覆盖的未覆盖区域。

公开(公告)号：US20150364260A1

公开(公告)日：2015-12-17

申请号：US14833018

申请日：2015-08-21

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD

Inventor： Byoung Hwa LEE ,  Kyo Kwang LEE ,  Min Cheol PARK ,  Young Ghyu AHN ,  Sang Soo PARK

IPC: H01G4/30 ,  H05K1/11 ,  H01G4/008 ,  H01G4/248 ,  H05K1/18 ,  H01G4/12

CPC classification number: H01G4/30 ,  H01G2/065 ,  H01G4/008 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248 ,  H05K1/111 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A multilayer ceramic capacitor may include: three external electrodes disposed on a mounting surface of a ceramic body to be spaced apart from one another. When a thickness of an active layer including a plurality of first and second internal electrodes disposed therein is defined as AT, and a gap between a first or second lead part of the first internal electrode and a third lead part of the second internal electrode is defined as LG, the following Equation may be satisfied: 0.00044≦LG*log[1/AT]≦0.00150.

Abstract translation: 多层陶瓷电容器可以包括：三个外部电极，设置在彼此间隔开的陶瓷体的安装表面上。 当将包括设置在其中的多个第一和第二内部电极的有源层的厚度定义为AT时，并且限定第一内部电极的第一或第二引线部分与第二内部电极的第三引线部分之间的间隙 作为LG，可以满足以下等式：0.00044＆nlE; LG * log [1 / AT]＆nlE; 0.00150。

公开(公告)号：US09208947B2

公开(公告)日：2015-12-08

申请号：US14086962

申请日：2013-11-21

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Dong Su Cho ,  Hyun Woo Kim

IPC: H01G4/06 ,  H01G4/12 ,  H01G4/30 ,  H01G2/06 ,  H05K1/18

CPC classification number: H01G4/12 ,  H01G2/06 ,  H01G4/30 ,  H05K1/185 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611

Abstract: There is provided a multilayer ceramic capacitor, including a ceramic body including a plurality of dielectric layers stacked in a width direction and having upper and lower surface, first and second side surfaces, and first and second end surfaces, a first internal electrode formed on the dielectric layer and including a first lead part exposed to the upper and lower surfaces, a second internal electrode facing the first internal electrode, having at least one dielectric layer therebetween and having a second lead part exposed to the upper and lower surfaces, a first external electrode, a second external electrode, a first dummy pattern, and a second dummy pattern, wherein when a length of the ceramic body is B, a distance of the first lead part is C1, and a distance of the first dummy pattern is C3, 0.1≦(C1+C3)/B≦0.6 is satisfied.

Abstract translation: 提供了一种多层陶瓷电容器，其包括陶瓷体，该陶瓷体包括沿宽度方向堆叠的多个电介质层，具有上表面和下表面，第一和第二侧表面以及第一和第二端表面，形成在第一和第二端面上的第一内部电极 电介质层，并且包括暴露于上表面和下表面的第一引线部分，面对第一内部电极的第二内部电极，其间具有至少一个电介质层，并且具有暴露于上表面和下表面的第二引线部分，第一外部电极 电极，第二外部电极，第一虚设图案和第二虚设图案，其中当陶瓷体的长度为B时，第一引线部分的距离为C1，第一虚设图案的距离为C3， 0.1＆nlE;（C1 + C3）/B&nlE .0.6。

公开(公告)号：US09179549B2

公开(公告)日：2015-11-03

申请号：US12967791

申请日：2010-12-14

Applicant: Shih-Ping Hsu ,  Zhao-Chong Zeng

Inventor： Shih-Ping Hsu ,  Zhao-Chong Zeng

IPC: H05K1/16 ,  H05K1/18 ,  H05K3/46 ,  H01L23/498

CPC classification number: H05K3/32 ,  H01L23/49822 ,  H01L2924/00013 ,  H01L2924/0002 ,  H05K1/186 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: A packaging substrate includes: a core board with at least a cavity; a dielectric layer unit having upper and lower surfaces and encapsulating the core board and filling the cavity; a plurality of positioning pads embedded in the lower surface of the dielectric layer unit; at least a passive component having upper and lower surfaces with electrode pads disposed thereon and embedded in the dielectric layer unit so as to be received in the cavity of the core board at a position corresponding to the positioning pads; first and second wiring layers disposed on the upper and lower surfaces of the dielectric layer unit and electrically connected to the electrode pads of the upper and lower surfaces of the passive component through conductive vias, respectively. By embedding the passive component in the core board and the dielectric layer unit, the invention effectively reduces the height of the overall structure.

Abstract translation: 封装基板包括：具有至少空腔的芯板; 介电层单元，具有上表面和下表面并且封装所述芯板并填充所述空腔; 多个定位焊盘，其嵌入在所述电介质层单元的下表面中; 至少一个无源部件，具有上表面和下表面，其上设置有电极焊盘并且嵌入在电介质层单元中，以便在对应于定位焊盘的位置处容纳在芯板的空腔中; 第一和第二布线层分别设置在电介质层单元的上表面和下表面上，并分别通过导电通孔与无源部件的上表面和下表面的电极焊盘电连接。 通过将无源部件嵌入在核心板和电介质层单元中，本发明有效地降低了整体结构的高度。

公开(公告)号：US09159697B2

公开(公告)日：2015-10-13

申请号：US14219042

申请日：2014-03-19

Applicant: Wistron Corporation

Inventor： Hui-Ying Chou ,  Lee-Chieh Kang

IPC: H01L21/4763 ,  H01L21/44 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L24/81 ,  H01L23/13 ,  H01L23/528 ,  H01L23/53204 ,  H05K3/0005 ,  H05K3/3442 ,  H05K3/4007 ,  H05K2201/0969 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A method for forming voids corresponding to pads of SMT components is provided. The method comprises following steps: One or more condition parameters are inputted into a searching unit. The searching unit searches all of the pads with reference to the condition parameters to obtain a pre-selected group of pads. A judgment unit is provided to determine whether each pad of the pre-selected group of pads meets a pre-determined processing requirement to generate a to-be-processed group of pads. An execution unit executes a void formation step with reference to corner coordinates of each of the to-be-processed group of pads, so as to form at least a void at the portion of a contact surface corresponding to a corner of the pad. In an embodiment, four voids which are related to respective corners of each pad of the to-be-processed group are formed at the contact surface accordingly.

Abstract translation: 提供了一种形成对应于SMT部件的焊盘的空隙的方法。 该方法包括以下步骤：将一个或多个条件参数输入到搜索单元。 参考条件参数，搜索单元搜索所有的焊盘，以获得预选的焊盘组。 提供判断单元以确定预先选择的焊盘组中的每个焊盘是否满足预定的处理要求以生成要处理的焊盘组。 执行单元参照要处理的一组焊盘的角坐标来执行空隙形成步骤，以便在与焊盘的角部相对应的接触表面的部分处形成至少一个空隙。 在一个实施例中，相应地在接触表面处形成与被处理组的每个焊盘的各个角相关的四个空隙。

公开(公告)号：US20150287532A1

公开(公告)日：2015-10-08

申请号：US14667928

申请日：2015-03-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroshi ABE ,  Yoshiyuki NOMURA ,  Junichi SAITO

IPC: H01G4/224 ,  H01G4/008 ,  H01G4/248 ,  H01G4/12 ,  H05K1/18 ,  H01G4/30

CPC classification number: H01G4/224 ,  H01G2/065 ,  H01G4/232 ,  H01G4/2325 ,  H01G4/248 ,  H01G4/30 ,  H01G13/003 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/0769 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic component includes a main body, first and second external electrodes, and a water-repellent film. The first and second external electrodes are provided on a portion of a surface of the main body. The water-repellent film is provided on another portion of the surface of the main body and on a surface of the first external electrode. The water-repellent film contains a non-cross-linked silicone resin. An angle of contact of water of about 25° C. with the water-repellent film is not less than about 100° and not greater than about 160°.

Abstract translation: 电子部件包括主体，第一和第二外部电极以及防水膜。 第一外部电极和第二外部电极设置在主体的表面的一部分上。 防水膜设置在主体的表面的另一部分和第一外部电极的表面上。 防水膜含有非交联的有机硅树脂。 约25℃的水与防水膜的接触角度不小于约100°且不大于约160°。

公开(公告)号：US20150282305A1

公开(公告)日：2015-10-01

申请号：US14669329

申请日：2015-03-26

Applicant: IBIDEN CO., LTD.

Inventor： Toyotaka SHIMABE ,  Shunsuke SAKAI

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/18

CPC classification number: H05K1/0284 ,  H01L21/568 ,  H01L24/19 ,  H01L24/25 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/2518 ,  H01L2224/82039 ,  H01L2924/15313 ,  H05K1/185 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/0344 ,  H05K2201/09036 ,  H05K2201/09145 ,  H05K2201/09154 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913

Abstract: A multilayer wiring board with a built-in electronic component includes a substrate, a conductor layer formed on surface of the substrate, one or more electronic components positioned in a cavity formed through the substrate, an insulating layer formed on the substrate such that the insulating layer is formed on the component in the cavity, and a wiring layer formed on the insulating layer. The conductor layer has an opening formed such that the cavity is formed in the opening of the conductor layer and that the conductor layer has a first side in the opening and a second side in the opening on the opposite side across the cavity, and the cavity is formed in the opening of the conductor layer such that width between the cavity and the first side of the conductor layer is greater than width between the cavity and the second side of the conductor layer.

Abstract translation: 具有内置电子部件的多层布线基板包括基板，形成在基板的表面上的导体层，位于通过基板形成的空腔中的一个或多个电子部件，形成在基板上的绝缘层， 在空腔中的部件上形成层，以及形成在绝缘层上的布线层。 导体层具有形成为使得空腔形成在导体层的开口中并且导体层在开口中具有第一侧的开口，并且在开口中的相对于空腔的开口中的第二侧，并且空腔 形成在导体层的开口中，使得空腔和导体层的第一侧之间的宽度大于导体层的空腔和第二侧之间的宽度。

公开(公告)号：US20150245492A1

公开(公告)日：2015-08-27

申请号：US14626085

申请日：2015-02-19

Applicant: IBIDEN CO., LTD.

Inventor： Toyotaka SHIMABE ,  Toshiki Furutani ,  Shunsuke Sakai

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/568 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/82039 ,  H01L2924/153 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09827 ,  H05K2201/09972 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A multilayer wiring board with built-in electronic components includes a substrate including an insulating material and having multiple opening portions, a first conductor layer formed on a surface of the substrate and having an opening portion such that the substrate has the opening portions inside the opening portion of the first conductor layer, multiple electronic components positioned in the opening portions of the substrate, and an insulating layer formed on the substrate such that the insulating layer is formed on the electronic components and on the first conductor layer. The opening portions are formed in the substrate such that the opening portions include two opening portions and that the substrate has a partition wall formed between the two opening portions.

Abstract translation: 具有内置电子部件的多层布线基板包括具有绝缘材料并具有多个开口部的基板，形成在基板的表面上的具有开口部的第一导体层，使得基板在开口部内部具有开口部 第一导体层的一部分，位于基板的开口部的多个电子部件和形成在基板上的绝缘层，使得绝缘层形成在电子部件上和第一导体层上。 开口部形成在基板上，使得开口部分包括两个开口部分，并且基板具有形成在两个开口部之间的分隔壁。

公开(公告)号：US09119299B2

公开(公告)日：2015-08-25

申请号：US12309118

申请日：2006-07-21

Applicant: Oskar Schallmoser

Inventor： Oskar Schallmoser

IPC: H05K1/16 ,  H05K1/02

CPC classification number: H05K1/0271 ,  H05K1/0231 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/1003 ,  H05K2201/10636 ,  H05K2201/2045 ,  Y02P70/611

Abstract: Surface mounted ceramic capacitors (14) on printed circuit boards (10′) are subject to vibrations (18) caused by the piezo effect. Other electronic components are subject to magnetostriction and likewise generate vibrations. In prior art, the vibrations can propagate (20) on a printed circuit board (10). To suppress the propagation of the vibrations caused by the electronic component (14), the invention provides at least one slot (22) in the printed circuit board (10′). The slot (22) extends, for example, parallel to a side wall of the electronic component (14).

Abstract translation: 印刷电路板（10'）上的表面安装陶瓷电容器（14）受到由压电效应引起的振动（18）。 其他电子元件会受到磁致伸缩的影响，并产生振动。 在现有技术中，振动可以在印刷电路板（10）上传播（20）。 为了抑制由电子部件（14）引起的振动的传播，本发明在印刷电路板（10'）中提供至少一个槽（22）。 槽（22）例如平行于电子部件（14）的侧壁延伸。