公开(公告)号：US20100007015A1

公开(公告)日：2010-01-14

申请号：US12171759

申请日：2008-07-11

Applicant: Bernardo Gallegos

Inventor： Bernardo Gallegos

IPC: H01L23/488 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81385 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/01014 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An integrated circuit device (300) includes a functional integrated circuit (IC) die (310) having a top IC surface with IC non-contact regions (313) and a plurality of electrically conductive bump pads (311, 312, 313) at pad locations. In the IC (310), at least one of the bump pads (311, 312, 313) extends outward from beyond the IC non-contact regions (313). The integrated circuit device (300) can also include a workpiece (305) having a top workpiece surface comprising at least one die attach area (319) for attaching the IC die (310). The die attach area (319) can include non-contact regions (316) and a plurality of electrically conductive contact pads (317) recessed relative to the non-contact regions (316), where the contact pads (317) face the top IC surface and match the pad locations (312). In the die attach area (319), at least one of the contact pads (317) includes electrically conductive pedestal features (321) extending towards the top IC surface, where the extending bump pads (311) physically contact one of the pedestal features (321) and electrically connect the IC die (310) to the workpiece (305). In the integrated circuit device (300), the pedestal features (321) increase a gap between the IC (310) and the workpiece top surfaces to be filled with an underfill dielectric material (332).

Abstract translation: 集成电路器件（300）包括功能集成电路（IC）管芯（310），其具有具有IC非接触区域（313）的顶部IC表面和在焊盘处的多个导电凸块焊盘（311,312,313） 位置。 在IC（310）中，凸块焊盘（311,312,313）中的至少一个从IC非接触区域（313）的外部向外延伸。 集成电路器件（300）还可以包括具有顶部工件表面的工件（305），该工件表面包括用于附接IC管芯（310）的至少一个管芯附着区域（319）。 管芯附着区域（319）可以包括非接触区域（316）和相对于非接触区域（316）凹陷的多个导电接触焊盘（317），其中接触焊盘（317）面向顶部IC 表面并匹配焊盘位置（312）。 在管芯附着区域（319）中，至少一个接触焊盘（317）包括朝向顶部IC表面延伸的导电基座特征（321），其中延伸的凸块焊盘（311）物理接触基座特征之一 321）并且将IC管芯（310）电连接到工件（305）。 在集成电路器件（300）中，基座特征（321）增加了IC（310）和待填充的底部填充介电材料（332）的工件顶表面之间的间隙。

公开(公告)号：US20090302463A1

公开(公告)日：2009-12-10

申请号：US12136231

申请日：2008-06-10

Applicant: BERNARDO GALLEGOS ,  DONALD C. ABBOTT

Inventor： BERNARDO GALLEGOS ,  DONALD C. ABBOTT

IPC: H01L23/48 ,  H01L21/58

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/108 ,  H05K3/3452 ,  H05K3/3473 ,  H05K3/386 ,  H05K3/423 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/10674 ,  H05K2203/063 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device having an insulating substrate with differentially plated metal and selective solder. Chip 221 with contact studs 223 is attached onto the traces 203 on tape 101. The traces, which are unprotected by soldermask 110, have solder on the top surface, but not on the sidewalls. The sidewalls of the traces are at right angles to the trace top, giving the trace a rectangular cross section. Consequently, the area for attaching stud 223 is maximized. At the same time, the differential plating method of trace metal 203 and through-hole metal 206 allows different metal thicknesses and provides independent control of the trace aspect ratio for low electrical resistance and trace fatigue.

Abstract translation: 具有绝缘基板的半导体器件，具有差分镀金属和选择性焊料。 具有接触柱223的芯片221附着在磁带101上的迹线203上。未被焊接掩模110保护的迹线在顶表面上具有焊料，但不在侧壁上。 迹线的侧壁与轨迹顶部成直角，给出轨迹为矩形截面。 因此，用于安装螺柱223的区域最大化。 同时，痕量金属203和通孔金属206的差分电镀方法允许不同的金属厚度，并且对于低电阻和痕量疲劳提供独立的痕量纵横比的控制。

公开(公告)号：US20130075890A1

公开(公告)日：2013-03-28

申请号：US13481275

申请日：2012-05-25

Applicant: Bernardo Gallegos ,  Abram Castro

Inventor： Bernardo Gallegos ,  Abram Castro

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L21/76858 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4871 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76885 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/03436 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Integrated circuits and methods of fabricating integrated circuits are disclosed herein. One embodiment of an integrated circuit includes a die having a side, wherein a conductive stud extends substantially normal relative to the side. A dielectric layer having a first side and a second side is located proximate the side of the die so that the first side of the dielectric layer is adjacent the side of the die. The conductive stud extends into the first side of the dielectric layer. A first via extends between the conductive stud and the second side of the dielectric layer. A conductive layer having a first side and a second side is located adjacent the second side of the dielectric layer, wherein the first side of the conductive layer is located adjacent the second side of the dielectric layer. At least a portion of the conductive layer is electrically connected to the first via.

Abstract translation: 本文公开了集成电路和制造集成电路的方法。 集成电路的一个实施例包括具有侧面的管芯，其中导电突出部相对于侧面基本上正常地延伸。 具有第一侧和第二侧的电介质层位于模具的侧面附近，使得电介质层的第一侧与模具的侧面相邻。 导电螺柱延伸到电介质层的第一侧。 第一通孔延伸在导电柱和电介质层的第二侧之间。 具有第一侧和第二侧的导电层位于电介质层的第二侧附近，其中导电层的第一侧位于电介质层的第二侧附近。 导电层的至少一部分电连接到第一通孔。

公开(公告)号：US08298874B2

公开(公告)日：2012-10-30

申请号：US13526116

申请日：2012-06-18

Applicant: Bernardo Gallegos ,  Kenji Masumoto

Inventor： Bernardo Gallegos ,  Kenji Masumoto

IPC: H01L21/00

CPC classification number: H01L23/49816 ,  H01L21/563 ,  H01L23/13 ,  H01L23/295 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/1134 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/13583 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for forming a packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. A second dielectric layer is formed on the top substrate surface of the package substrate. An IC die which is mounted to the top substrate surface of the package substrate. An underfill layer is formed between the IC die and the die attach region.

Abstract translation: 一种用于形成封装的电子器件的方法，其包括具有顶部衬底表面的封装衬底，所述顶部衬底表面包括其上包括至少一个焊盘焊盘的焊盘附着区域和位于焊盘焊盘侧面的第一电介质层和非裸片附着区域。 第二电介质层形成在封装衬底的顶部衬底表面上。 安装在封装基板的顶部基板表面上的IC管芯。 在IC管芯和管芯附着区域之间形成底层填充层。

公开(公告)号：US20120252170A1

公开(公告)日：2012-10-04

申请号：US13526116

申请日：2012-06-18

Applicant: Bernardo Gallegos ,  Kenji Masumoto

Inventor： Bernardo Gallegos ,  Kenji Masumoto

IPC: H01L21/56

CPC classification number: H01L23/49816 ,  H01L21/563 ,  H01L23/13 ,  H01L23/295 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/1134 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/13583 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for forming a packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. A second dielectric layer is formed on the top substrate surface of the package substrate. An IC die which is mounted to the top substrate surface of the package substrate. An underfill layer is formed between the IC die and the die attach region.

Abstract translation: 一种用于形成封装的电子器件的方法，其包括具有顶部衬底表面的封装衬底，所述顶部衬底表面包括其上包括至少一个焊盘焊盘的焊盘附着区域和位于焊盘焊盘侧面的第一电介质层和非裸片附着区域。 第二电介质层形成在封装衬底的顶部衬底表面上。 安装在封装基板的顶部基板表面上的IC管芯。 在IC管芯和管芯附着区域之间形成底层填充层。

公开(公告)号：US20110177686A1

公开(公告)日：2011-07-21

申请号：US13074227

申请日：2011-03-29

Applicant: Kejun ZENG ,  Wei Qun PENG ,  Rebecca L. HOLFORD ,  Robert John FURTAW ,  Bernardo GALLEGOS

Inventor： Kejun ZENG ,  Wei Qun PENG ,  Rebecca L. HOLFORD ,  Robert John FURTAW ,  Bernardo GALLEGOS

IPC: H01L21/60

CPC classification number: H01L24/81 ,  B23K1/0016 ,  B23K35/007 ,  B23K35/262 ,  B23K35/286 ,  B23K35/3013 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13583 ,  H01L2224/136 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/013

Abstract: A metallic interconnect structure (200) for connecting a gold bump (205) and a contact pad (212), as used for example in semiconductor flip-chip assembly. A first region (207) of binary AuSn2 intermetallic is adjacent to the gold bump. A region (208) of binary AuSn4 intermetallic is adjacent to the first AuSn2 region. Then, a region (209) of binary gold-tin solid solution is adjacent to the AuSn4 region, and a second region (210) of binary AuSn2 intermetallic is adjacent to the solid solution region. The second AuSn2 region is adjacent to a nickel layer (213) (preferred thickness about 0.08 μm), which covers the copper pad. The nickel layer insures that the gold/tin intermetallics and solutions remain substantially free of copper and thus avoid ternary compounds, providing stabilized gold bump/solder connections.

Abstract translation: 用于连接金凸块（205）和接触垫（212）的金属互连结构（200），例如用于半导体倒装芯片组装。 二元AuSn2金属间化合物的第一区域（207）与金凸块相邻。 二元AuSn4金属间化合物的区域（208）与第一AuSn2区相邻。 然后，二元金 - 锡固溶体的区域（209）与AuSn4区相邻，并且二元AuSn2金属间化合物的第二区（210）与固溶区相邻。 第二AuSn2区域邻近覆盖铜焊盘的镍层（213）（优选厚度约0.08μm）。 镍层确保金/锡金属间化合物和溶液基本上不含铜，从而避免三元化合物，提供稳定的金凸块/焊料连接。

公开(公告)号：US07851928B2

公开(公告)日：2010-12-14

申请号：US12136231

申请日：2008-06-10

Applicant: Bernardo Gallegos ,  Donald C. Abbott

Inventor： Bernardo Gallegos ,  Donald C. Abbott

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/108 ,  H05K3/3452 ,  H05K3/3473 ,  H05K3/386 ,  H05K3/423 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/10674 ,  H05K2203/063 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device having an insulating substrate with differentially plated metal and selective solder. Chip 221 with contact studs 223 is attached onto the traces 203 on tape 101. The traces, which are unprotected by soldermask 110, have solder on the top surface, but not on the sidewalls. The sidewalls of the traces are at right angles to the trace top, giving the trace a rectangular cross section. Consequently, the area for attaching stud 223 is maximized. At the same time, the differential plating method of trace metal 203 and through-hole metal 206 allows different metal thicknesses and provides independent control of the trace aspect ratio for low electrical resistance and trace fatigue.

Abstract translation: 具有绝缘基板的半导体器件，具有差分镀金属和选择性焊料。 具有接触柱223的芯片221附着在磁带101上的迹线203上。未被焊接掩模110保护的迹线在顶表面上具有焊料，但不在侧壁上。 迹线的侧壁与轨迹顶部成直角，给出轨迹为矩形截面。 因此，用于安装螺柱223的区域最大化。 同时，痕量金属203和通孔金属206的差分电镀方法允许不同的金属厚度，并且对于低电阻和痕量疲劳提供独立的痕量纵横比的控制。

公开(公告)号：US20090091024A1

公开(公告)日：2009-04-09

申请号：US11867051

申请日：2007-10-04

Applicant: Kejun Zeng ,  Wei Qun Peng ,  Rebecca L. Holford ,  Robert John Furtaw ,  Bernardo Gallegos

Inventor： Kejun Zeng ,  Wei Qun Peng ,  Rebecca L. Holford ,  Robert John Furtaw ,  Bernardo Gallegos

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L24/81 ,  B23K1/0016 ,  B23K35/007 ,  B23K35/262 ,  B23K35/286 ,  B23K35/3013 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13583 ,  H01L2224/136 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/013

Abstract: A metallic interconnect structure (200) for connecting a gold bump (205) and a copper pad (212), as used for example in semiconductor flip-chip assembly. A first region (207) of binary AuSn2 intermetallic is adjacent to the gold bump. A region (208) of binary AuSn4 intermetallic is adjacent to the first AuSn2 region. Then, a region (209) of binary gold-tin solid solution is adjacent to the AuSn4 region, and a second region (210) of binary AuSn2 intermetallic is adjacent to the solid solution region. The second AuSn2 region is adjacent to a nickel layer (213) (preferred thickness about 0.08 μm), which covers the copper pad. The nickel layer insures that the gold/tin intermetallics and solutions remain substantially free of copper and thus avoid ternary compounds, providing stabilized gold bump/solder connections.

Abstract translation: 金属互连结构（200），用于连接例如半导体倒装芯片组装中的金凸块（205）和铜焊盘（212）。 二元AuSn2金属间化合物的第一区域（207）与金凸块相邻。 二元AuSn4金属间化合物的区域（208）与第一AuSn2区相邻。 然后，二元金 - 锡固溶体的区域（209）与AuSn4区相邻，并且二元AuSn2金属间化合物的第二区（210）与固溶区相邻。 第二AuSn2区域与覆盖铜焊盘的镍层（213）（优选厚度约0.08μm）相邻。 镍层确保金/锡金属间化合物和溶液基本上不含铜，从而避免三元化合物，提供稳定的金凸块/焊料连接。

公开(公告)号：US20130075894A1

公开(公告)日：2013-03-28

申请号：US13563345

申请日：2012-07-31

Applicant: Bernardo Gallegos ,  Abram Castro

Inventor： Bernardo Gallegos ,  Abram Castro

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L21/76838 ,  H01L21/56 ,  H01L21/76801 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/12105 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/9202 ,  H01L2924/15311 ,  H01L2224/13347 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Integrated circuits and methods of fabricating integrated circuits are disclosed herein. One embodiment of an integrated circuit includes a die having a side, wherein a conductive stud extends from the side. A dielectric layer having a first side and a second side is located proximate the side of the die so that the first side of the dielectric layer is adjacent the side of the die. The conductive stud extends into the first side of the dielectric layer. A conductive layer having a first side and a second side is located adjacent the second side of the dielectric layer, wherein the first side of the conductive layer is located adjacent the second side of the dielectric layer. A conductive adhesive connects the conductive stud to the first side of the conductive layer.

Abstract translation: 本文公开了集成电路和制造集成电路的方法。 集成电路的一个实施例包括具有侧面的模具，其中导电柱从侧面延伸。 具有第一侧和第二侧的电介质层位于模具的侧面附近，使得电介质层的第一侧与模具的侧面相邻。 导电螺柱延伸到电介质层的第一侧。 具有第一侧和第二侧的导电层位于电介质层的第二侧附近，其中导电层的第一侧位于电介质层的第二侧附近。 导电粘合剂将导电柱连接到导电层的第一侧。

公开(公告)号：US20100301493A1

公开(公告)日：2010-12-02

申请号：US12563206

申请日：2009-09-21

Applicant: BERNARDO GALLEGOS ,  KENJI MASUMOTO

Inventor： BERNARDO GALLEGOS ,  KENJI MASUMOTO

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/49816 ,  H01L21/563 ,  H01L23/13 ,  H01L23/295 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/1134 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/13583 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. The non-die attach region includes a second dielectric layer, wherein a thickness of the second dielectric layer is>a thickness of the first dielectric layer by at least 5 μm. An IC die has a top semiconductor surface including active circuitry and at least one bonding conductor formed on the top semiconductor surface, and a bottom surface, wherein the bonding conductor of the IC die is joined to the land pad of the package substrate. An underfill layer is between the IC die and the die attach region.

Abstract translation: 一种封装电子器件，包括具有顶部衬底表面的封装衬底，所述顶部衬底表面包括其上包括至少一个焊盘焊盘的管芯附着区域和位于焊盘焊盘侧面的第一电介质层和非裸片附着区域。 非芯片附着区域包括第二电介质层，其中第二电介质层的厚度>第一介电层的厚度>至少5μm。 IC芯片具有包括有源电路和形成在顶部半导体表面上的至少一个接合导体的顶部半导体表面和底表面，其中IC芯片的接合导体接合到封装衬底的焊盘。 芯片和芯片附着区域之间的底层填充层。