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公开(公告)号：US07811626B2
公开(公告)日：2010-10-12
申请号：US12328077
申请日：2008-12-04
Applicant: Chang-soo Jang , Dong-kwan Won , Hyoung-ho Roh , Jae-chul Ryu
Inventor： Chang-soo Jang , Dong-kwan Won , Hyoung-ho Roh , Jae-chul Ryu
IPC: B05D5/12
CPC classification number: H05K1/0366 , H05K3/022 , H05K2203/1545 , Y10S428/901 , Y10T428/24917 , Y10T428/24926
Abstract: Provided is a method of manufacturing a printed circuit board. In an embodiment, the method includes forming a prepreg layer via a reel method, forming a conductive film for forming a circuit pattern on at least one surface of the prepreg layer; and forming a predetermined circuit pattern on the conductive film. In an embodiment, the prepreg layer has a thickness of at most about 0.15 mm and contains a fiber material and a resin material. In an embodiment, the content of the resin material in the prepreg layer is about 70% or less by volume. In an embodiment, the prepreg layer is composed of at least one prepreg layer.
Abstract translation: 提供一种制造印刷电路板的方法。 在一个实施例中，该方法包括通过卷轴方法形成预浸料层，在预浸料层的至少一个表面上形成用于形成电路图案的导电膜; 并在导电膜上形成预定的电路图案。 在一个实施例中，预浸料层具有至多约0.15mm的厚度，并且包含纤维材料和树脂材料。 在一个实施方式中，预浸料层中的树脂材料的含量为约70体积％以下。 在一个实施例中，预浸料层由至少一个预浸料层组成。
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公开(公告)号：US07470461B2
公开(公告)日：2008-12-30
申请号：US11244649
申请日：2005-10-05
Applicant: Chang-soo Jang , Dong-kwan Won , Hyoung-ho Roh , Jae-chul Ryu
Inventor： Chang-soo Jang , Dong-kwan Won , Hyoung-ho Roh , Jae-chul Ryu
IPC: B32B3/00
CPC classification number: H05K1/0366 , H05K3/022 , H05K2203/1545 , Y10S428/901 , Y10T428/24917 , Y10T428/24926
Abstract: Provided is a method of manufacturing a printed circuit board. In an embodiment, the method includes forming a prepreg layer via a reel method, forming a conductive film for forming a circuit pattern on at least one surface of the prepreg layer; and forming a predetermined circuit pattern on the conductive film. In an embodiment, the prepreg layer has a thickness of at most about 0.15 mm and contains a fiber material and a resin material. In an embodiment, the content of the resin material in the prepreg layer is about 70% or less by volume. In an embodiment, the prepreg layer is composed of at least one prepreg layer.
Abstract translation: 提供一种制造印刷电路板的方法。 在一个实施例中，该方法包括通过卷轴方法形成预浸料层，在预浸料层的至少一个表面上形成用于形成电路图案的导电膜; 并在导电膜上形成预定的电路图案。 在一个实施例中，预浸料层具有至多约0.15mm的厚度，并且包含纤维材料和树脂材料。 在一个实施方式中，预浸料层中的树脂材料的含量为约70体积％以下。 在一个实施例中，预浸料层由至少一个预浸料层组成。
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公开(公告)号：US20060038280A1
公开(公告)日：2006-02-23
申请号：US11133727
申请日：2005-05-20
Applicant: Chang-soo Jang , Jae-chul Ryu , Dong-kwan Won
Inventor： Chang-soo Jang , Jae-chul Ryu , Dong-kwan Won
CPC classification number: H01L23/49838 , H01L23/13 , H01L23/145 , H01L23/49827 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/49175 , H01L2224/73215 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01058 , H01L2924/01078 , H01L2924/01087 , H01L2924/07802 , H01L2924/15311 , H01L2924/19041 , H05K1/0271 , H05K3/0052 , H05K3/28 , H05K2201/068 , H05K2201/09781 , H05K2203/1572 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A parent or master substrate for a semiconductor package is provided, which can provide a plurality of unit substrates by cutting into pieces for producing a semiconductor device. The parent substrate includes an insulation layer, conductor patterns formed on first and second surfaces of the insulation layer, and PSR (photo solder resist) layers respectively formed on the first and second surfaces of the insulation layers and covering the conductor patterns. The parent substrate includes an upper part and a lower part divided by a reference surface which passes through the center of the insulation layer. When an equivalent thermal expansion coefficient αupper of the upper part is defined by the Equation of α upper = ∑ i = 1 n α i × E i × v i ∑ i = 1 n E i × v i , where αi is respective thermal expansion coefficients of, Ei is respective elastic moduli of, and vi is respective volume ratios of first through nth components constituting the upper part (e.g., insulation layer, conductor patterns, and PSR layers of the upper part), and an equivalent thermal expansion coefficient αlower of the lower part is defined by the Equation of α lower = ∑ j = 1 m α j × E j × v j ∑ j = 1 m E j × v j , where αj is respective thermal expansion coefficients of, Ej is respective elastic moduli of, and vj is respective volume ratios of first through mth components constituting the lower part (e.g., insulation layer, conductor patterns, and PSR layers of the lower part), a equivalent thermal expansion ratio (αupper/αlower) of αupper to αlower is selected to be within a range of 0.975 through 1.165.
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4.发明授权Method for measuring analog channel resistance of a semiconductor device having a gate, a source, a drain, a drain sense and a source sense 失效用于测量具有栅极，源极，漏极，漏极感测和源极感测的半导体器件的模拟沟道电阻的方法公开(公告)号：US07615991B2
公开(公告)日：2009-11-10
申请号：US11892753
申请日：2007-08-27
Applicant: Chang Soo Jang
Inventor： Chang Soo Jang
CPC classification number: G01R31/2621 , H01L22/14 , H01L29/41725 , H01L29/78
Abstract: A semiconductor device and a method for measuring an analog channel resistance thereof are provided. The semiconductor device includes a substrate, a gate insulating layer and a gate formed on the substrate, a source and a drain formed in the substrate and at both sides of the gate, a source sense connected to the source, and a drain sense connected to the drain.
Abstract translation: 提供了一种用于测量其模拟通道电阻的半导体器件和方法。 半导体器件包括衬底，栅极绝缘层和形成在衬底上的栅极，形成在衬底中并位于栅极两侧的源极和漏极，连接到源极的源极检测器以及与源极连接的漏极检测器 排水。
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5.发明授权Method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device 失效测量MOS晶体管器件中栅极氧化物的平带状态电容的方法公开(公告)号：US07315174B2
公开(公告)日：2008-01-01
申请号：US11646515
申请日：2006-12-28
Applicant: Chang Soo Jang
Inventor： Chang Soo Jang
CPC classification number: G01R31/2621 , G01R27/2605 , H01L22/14
Abstract: A method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device is disclosed. According to the method of measuring flat-band status capacitance of gate oxide in MOS transistor device, flat-band status capacitance of gate oxide in MOS transistor device can be automatically measured and immediately analyzed by using a characteristics measuring system that changes in accordance with a gate voltage.
Abstract translation: 公开了一种测量MOS晶体管器件中的栅极氧化物的平带状态电容的方法。 根据测量MOS晶体管器件中栅极氧化物的平带状态电容的方法，MOS晶体管器件中栅极氧化物的平带状态电容可以被自动测量并立即通过使用根据 栅极电压。
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Patent Agency Ranking
公开(公告)号：US07292138B2
公开(公告)日：2007-11-06
申请号：US11176104
申请日：2005-07-07
Applicant: Chang-soo Jang
Inventor： Chang-soo Jang
IPC: B60C23/00
CPC classification number: B60C13/00 , B29D2030/0077 , B60C19/00 , B60C23/0493
Abstract: Provided is a vehicle tire with an RFID tag. The damage of the RFID tag or non-recognition problem can be prevented when a severe operating atmosphere is applied to the tire. The RFID tag is mounted on a side of the tire, apart from a bead included on an inner circumference of the tire, within a distance of 0.74 in a radial direction from the bead toward a belt attached to an outer circumference of the tire assuming that the distance from the bead to the belt is 1.
Abstract translation: 具有RFID标签的车辆用轮胎。 当对轮胎施加严格的操作气氛时，可以防止RFID标签的损坏或不识别问题。 RFID标签安装在轮胎的一侧，除了包括在轮胎的内周上的胎圈之外，距离胎圈朝向轮胎的径向方向的距离为0.74的距离，假定如果 从胎圈到皮带的距离为1。
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7.发明申请Printed circuit board having structure for relieving stress concentration, and semiconductor chip package equipped with the same 有权具有缓解应力集中结构的印刷电路板，以及配备有该集成电路的半导体芯片封装公开(公告)号：US20060016619A1
公开(公告)日：2006-01-26
申请号：US11167858
申请日：2005-06-27
Applicant: Chang-soo Jang , Jae-chul Ryu , Seong-young Han
Inventor： Chang-soo Jang , Jae-chul Ryu , Seong-young Han
IPC: H05K7/06
CPC classification number: H01L23/49838 , H01L2924/0002 , H05K1/0271 , H05K1/111 , H05K1/189 , H05K2201/09781 , H05K2201/10674 , Y02P70/611 , H01L2924/00
Abstract: There are provided a printed circuit board having a structure for relieving a stress concentration on an outer most lead of leads, due to a difference in thermal expansion coefficients between the semiconductor device and the printed circuit board when the semiconductor device is mounted on the printed circuit board. The printed circuit board includes an inner lead portion to be connected to the semiconductor device. The inner lead portion includes a plurality of leads, arranged in parallel with a same pitch in a predetermined area, and additional leads located near both ends of the predetermined area in which the plurality of leads are arranged in parallel, respectively, wherein each of the plurality of leads has a pitch smaller than 30 μm and a width of the additional lead is wider than 20 μm. There are also provided a semiconductor chip package equipped with the printed circuit board according to the present invention.
Abstract translation: 由于半导体器件与印刷电路板之间的热膨胀系数不同，当半导体器件安装在印刷电路板上时，提供了一种印刷电路板，该印刷电路板具有用于消除引线外部引线上的应力集中的结构 板。 印刷电路板包括要连接到半导体器件的内引线部分。 内引线部分包括在预定区域中以相同间距平行布置的多个引线，以及分别位于多个引线平行布置的预定区域的两端附近的附加引线，其中每个引线 多个引线具有小于30μm的间距，并且附加引线的宽度大于20μm。 还提供了一种配备有根据本发明的印刷电路板的半导体芯片封装。
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8.发明授权Semiconductor device and method for measuring analog channel resistance thereof 失效用于测量其模拟通道电阻的半导体器件和方法公开(公告)号：US07898269B2
公开(公告)日：2011-03-01
申请号：US12568259
申请日：2009-09-28
Applicant: Chang Soo Jang
Inventor： Chang Soo Jang
CPC classification number: G01R31/2621 , H01L22/14 , H01L29/41725 , H01L29/78
Abstract: A semiconductor device and a method for measuring an analog channel resistance thereof are provided. The semiconductor device includes a substrate, a gate insulating layer and a gate formed on the substrate, a source and a drain formed in the substrate and at both sides of the gate, a source sense connected to the source, and a drain sense connected to the drain.
Abstract translation: 提供了一种用于测量其模拟通道电阻的半导体器件和方法。 半导体器件包括衬底，栅极绝缘层和形成在衬底上的栅极，形成在衬底中并位于栅极两侧的源极和漏极，连接到源极的源极检测器以及与源极连接的漏极检测器 排水。
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9.发明授权System and method for automatically measuring carrier density distribution by using capacitance-voltage characteristics of a MOS transistor device 失效通过使用MOS晶体管器件的电容电压特性来自动测量载流子密度分布的系统和方法公开(公告)号：US07489157B2
公开(公告)日：2009-02-10
申请号：US11646462
申请日：2006-12-28
Applicant: Chang Soo Jang
Inventor： Chang Soo Jang
CPC classification number: G01R31/2648
Abstract: Disclosed is a system and method for automatically measuring carrier density distribution by using capacitance-voltage characteristics of a MOS transistor device. System comprises an automatic probe station for measurement of an object wafer, the automatic probe station being electrically connected to the wafer; a capacitor measuring unit having a high frequency terminal and a low frequency terminal; and a control computer for being respectively connected the automatic probe station and the capacitor measuring unit, wherein the high frequency terminal is connected to a gate of the wafer and the low frequency terminal is connected to a substrate of the wafer.
Abstract translation: 公开了一种通过使用MOS晶体管器件的电容电压特性自动测量载流子密度分布的系统和方法。 系统包括用于测量物体晶片的自动探测台，该自动探测台电连接到晶片; 具有高频端子和低频端子的电容器测量单元; 以及控制计算机，用于分别连接自动探测站和电容测量单元，其中高频端子连接到晶片的栅极，低频端子连接到晶片的衬底。
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公开(公告)号：US20060105153A1
公开(公告)日：2006-05-18
申请号：US11244649
申请日：2005-10-05
Applicant: Chang-soo Jang , Jae-chul Ryu , Hyoung-ho Roh , Dong-kwan Won
Inventor： Chang-soo Jang , Jae-chul Ryu , Hyoung-ho Roh , Dong-kwan Won
IPC: B05D5/12
CPC classification number: H05K1/0366 , H05K3/022 , H05K2203/1545 , Y10S428/901 , Y10T428/24917 , Y10T428/24926
Abstract: Provided is a method of manufacturing a printed circuit board. In an embodiment, the method includes forming a prepreg layer via a reel method, forming a conductive film for forming a circuit pattern on at least one surface of the prepreg layer; and forming a predetermined circuit pattern on the conductive film. In an embodiment, the prepreg layer has a thickness of at most about 0.15 mm and contains a fiber material and a resin material. In an embodiment, the content of the resin material in the prepreg layer is about 70% or less by volume. In an embodiment, the prepreg layer is composed of at least one prepreg layer.
Abstract translation: 提供一种制造印刷电路板的方法。 在一个实施例中，该方法包括通过卷轴方法形成预浸料层，在预浸料层的至少一个表面上形成用于形成电路图案的导电膜; 并在导电膜上形成预定的电路图案。 在一个实施例中，预浸料层具有至多约0.15mm的厚度，并且包含纤维材料和树脂材料。 在一个实施方式中，预浸料层中的树脂材料的含量为约70体积％以下。 在一个实施例中，预浸料层由至少一个预浸料层组成。
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