公开(公告)号：US06942764B1

公开(公告)日：2005-09-13

申请号：US08518705

申请日：1995-08-24

Applicant: Cheng-Kun Lin ,  Chin-Shien Yang ,  Chuan-Huai Chen

Inventor： Cheng-Kun Lin ,  Chin-Shien Yang ,  Chuan-Huai Chen

IPC: C23C14/34 ,  H01L21/00

CPC classification number: H01J37/34 ,  H01J37/3411 ,  H01J37/3438 ,  H01J37/3476

Abstract: Contamination due to deposited particulate matter has been greatly reduced in single wafer sputter-etchers by coating the full interior of the sputtering shield with a layer of an arc-sprayed material such as aluminum, said layer being possessed of a high degree of surface roughness. The method for forming the coating of arc-sprayed aluminum is described and data comparing particulate contaminant count and product yield before and after the adoption of the present invention, are presented.

Abstract translation: 通过用诸如铝的电弧喷涂材料的层涂覆溅射屏蔽的全部内部，单晶片溅射蚀刻器中沉积的颗粒物质的污染已经大大降低，所述层具有高度的表面粗糙度。 介绍了形成电弧喷涂铝涂层的方法，并介绍了本发明采用前后颗粒污染物数量和产品产量的数据。

公开(公告)号：US06436253B1

公开(公告)日：2002-08-20

申请号：US09454655

申请日：1999-12-06

Applicant: Chin-Shien (Tony) Yang ,  Chuan-Huai Chen ,  Cheng-Kun Lin

Inventor： Chin-Shien (Tony) Yang ,  Chuan-Huai Chen ,  Cheng-Kun Lin

IPC: C23C1400

CPC classification number: H01J37/3244 ,  H01J37/34

Abstract: The uniformity of material removal, as well as contamination due to deposited particulate matter, has been reduced in single wafer sputter-etchers by providing an improved gas baffle. Said gas baffle presents a smooth surface to the incoming sputtering gas so that it disperses uniformly throughout the sputtering chamber, thereby avoiding local fluctuations in pressure which, in turn, can lead to local differences in material removal rate as well as to particulate contamination of the surface that is being etched. The design of the baffle is described along with a method for attaching it to the inside of the sputtering shield.

Abstract translation: 通过提供改进的气体挡板，在单晶片溅射蚀刻器中减少了材料去除的均匀性以及由于沉积的颗粒物质引起的污染。 所述气体挡板对进入的溅射气体呈现平滑的表面，使得其均匀地分散在整个溅射室中，从而避免局部的压力波动，这反过来可能导致材料去除速率的局部差异以及 被蚀刻的表面。 描述挡板的设计以及将其附接到溅射屏蔽件的内部的方法。

公开(公告)号：US06302948B1

公开(公告)日：2001-10-16

申请号：US09492860

申请日：2000-01-27

Applicant: Cheng Kun Lin ,  Chong Yu Chen ,  Wen Tung Chen ,  Shiau Yin Peggy Chang

Inventor： Cheng Kun Lin ,  Chong Yu Chen ,  Wen Tung Chen ,  Shiau Yin Peggy Chang

IPC: C09D1102

CPC classification number: D06P5/30

Abstract: The present invention relates to a textile ink-jet printing-purpose disperse dye micro-emulsion agent, which uses dispersing agents such as sodium polynaphthalene formaldehyde sulfonates, surfactants such as POE NP ether, and silicone derivative emulsion-type defoaming agents and bactericidal fungicidal agents for ink-jet CMYK four-color disperse dyes forming a stable dye micro-emulsion through micro-jetting homogenized emulsifier. This invention focuses on the disperse dyes suitable for polymers, applying a low-cost environmentally protective micro-emulsion agent in the ink protection technology so that the O/W model becomes a stable and homogenized system. This gives the textile ink-jet printing-purpose disperse dye micro-emulsion agent, with a dye particle diameter lying below 300 nm and high storage stability, rinse, sublimation, and light fastness over 4.

Abstract translation: 本发明涉及使用分散剂如聚萘二甲醛磺酸钠，表面活性剂如POE NP醚和硅氧烷衍生物乳液型消泡剂和杀菌杀真菌剂的纺织品喷墨印刷用分散染料微乳液剂 用于喷墨CMYK四色分散染料，通过微量喷射匀浆乳化剂形成稳定的染料微乳液。 本发明专注于适用于聚合物的分散染料，在油墨保护技术中应用低成本的环保微乳剂，使得O / W模型成为稳定和均匀的体系。 这给出纺织品喷墨印刷用分散染料微乳液，染料粒径低于300nm，储存稳定性高，漂洗，升华，耐光牢度超过4。

公开(公告)号：US06342135B1

公开(公告)日：2002-01-29

申请号：US08552245

申请日：1995-11-02

Applicant: Chin-Shien Yang ,  Chuan-Huai Chen ,  Cheng-Kun Lin

Inventor： Chin-Shien Yang ,  Chuan-Huai Chen ,  Cheng-Kun Lin

IPC: C23C1434

CPC classification number: H01J37/3244 ,  H01J37/34 ,  Y10T29/49

Abstract: The uniformity of material removal, as well as contamination due to deposited particulate matter, has been reduced in single wafer sputter-etchers by providing an improved gas baffle. Said gas baffle presents a smooth surface to the incoming sputtering gas so that it disperses uniformly throughout the sputtering chamber, thereby avoiding local fluctuations in pressure which, in turn, can lead to local differences in material removal rate as well as to particulate contamination of the surface that is being etched. The design of the baffle is described along with a method for attaching it to the inside of the sputtering shield.

公开(公告)号：US6060374A

公开(公告)日：2000-05-09

申请号：US090614

申请日：1998-06-04

Applicant: Cheng-Kun Lin ,  Szu-An Wu

Inventor： Cheng-Kun Lin ,  Szu-An Wu

IPC: H01L21/425

CPC classification number: H01L21/26506 ,  H01L21/28211 ,  H01L22/12

Abstract: Measurement of contaminating nitrogen during silicon ion implantation has been achieved by including a silicon wafer as a monitor in the implantation chamber. After silicon ion implantation, the monitor is subjected to a rapid thermal oxidation (about 1,100.degree. C. for one minute) and the thickness of the resulting grown oxide layer is measured. The thinner the oxide layer (relative to an oxide layer grown on pure silicon) the greater the degree of nitrogen contamination. For example, a reduction in oxide thickness of about 30 Angstroms corresponds to a nitrogen dosage of about 10.sup.13 atoms/sq. cm. By measuring total ion dosage during implantation and then subtracting the measured nitrogen dosage, the corrected silicon dosage may also be computed.

Abstract translation: 硅离子注入期间污染氮的测量已经通过将硅晶片作为监测器包括在注入室来实现。 在硅离子注入之后，将监测器进行快速热氧化（约1100℃1分钟），并测量所得生长的氧化物层的厚度。 氧化物层（相对于在纯硅上生长的氧化物层）越薄，氮污染程度越大。 例如，约30埃的氧化物厚度的减小对应于大约1013个原子/平方的氮剂量。 厘米。 通过测量植入期间的总离子剂量，然后减去测量的氮剂量，也可以计算校正的硅剂量。

公开(公告)号：US6030508A

公开(公告)日：2000-02-29

申请号：US83252

申请日：1998-05-20

Applicant: Chin-Shien Yang ,  Chuan-Huai Chen ,  Cheng-Kun Lin

Inventor： Chin-Shien Yang ,  Chuan-Huai Chen ,  Cheng-Kun Lin

IPC: H01J37/32 ,  H01J37/34 ,  C23C14/34

CPC classification number: H01J37/3244 ,  H01J37/34 ,  Y10T29/49

Abstract: The uniformity of material removal, as well as contamination due to deposited particulate matter, has been reduced in single wafer sputter-etchers by providing an improved gas baffle. Said gas baffle presents a smooth surface to the incoming sputtering gas so that it disperses uniformly throughout the sputtering chamber, thereby avoiding local fluctuations in pressure which, in turn, can lead to local differences in material removal rate as well as to particulate contamination of the surface that is being etched. The design of the baffle is described along with a method for attaching it to the inside of the sputtering shield.

Abstract translation: 通过提供改进的气体挡板，在单晶片溅射蚀刻器中减少了材料去除的均匀性以及由于沉积的颗粒物质引起的污染。 所述气体挡板对进入的溅射气体呈现平滑的表面，使得其均匀地分散在整个溅射室中，从而避免局部的压力波动，这反过来可能导致材料去除速率的局部差异以及 被蚀刻的表面。 描述挡板的设计以及将其附接到溅射屏蔽件的内部的方法。

公开(公告)号：US6037204A

公开(公告)日：2000-03-14

申请号：US131321

申请日：1998-08-07

Applicant: Shou-Zen Chang ,  Chaochieh Tsai ,  Chin-Hsiung Ho ,  Cheng Kun Lin

Inventor： Shou-Zen Chang ,  Chaochieh Tsai ,  Chin-Hsiung Ho ,  Cheng Kun Lin

IPC: H01L21/223 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/2236 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823835 ,  H01L29/665

Abstract: A method for forming salicide contacts and polycide conductive lines in integrated circuits is described which employs the ion implantation of both silicon and arsenic into polysilicon structures and into source/drain MOSFET elements is described. The method is effective in reducing gate-to-source/drain bridging in the manufacture of sub-micron CMOS integrated circuits and improving the conductivity of sub-micron wide polycide lines. Silicon is implanted into the polysilicon and into the source/drain surfaces forming a amorphized surface layer. Next a low dose, low energy arsenic implant is administered into the amorphized layer. The low dose shallow arsenic implant in concert with the amorphized layer initiates an equalized formation of titanium silicide over both NMOS and PMOS devices in CMOS integrated circuits without degradation of the PMOS devices. Amorphization by the electrically neutral silicon ions permits the use of a lower dose of arsenic than would be required if arsenic alone were implanted. In addition to amorphization, the implanted silicon prevents the formation of microvoids by providing silicon towards titanium silicide formation. The combined amorphization effect of the silicon and arsenic implants also facilitates a silicide phase transition on sub-micron wide polycide lines thereby improving their conductivity.

Abstract translation: 描述了在集成电路中形成硅化物接触和多硅化物导线的方法，其采用硅和砷的离子注入到多晶硅结构中并描述为源极/漏极MOSFET元件。 该方法在减少亚微米CMOS集成电路的制造中的栅极到源极/漏极桥接以及提高亚微米宽的多晶硅化物线的电导率方面是有效的。 将硅注入多晶硅并进入形成非晶化表面层的源极/漏极表面。 接下来，将低剂量的低能量砷植入物施用于非晶化层。 与非晶化层一致的低剂量浅砷植入物在CMOS集成电路中的NMOS和PMOS器件上均衡形成钛硅化物，而不会降低PMOS器件。 通过电中性硅离子的非晶化允许使用比单独砷植入所需的更低剂量的砷。 除了非晶化之外，注入的硅通过向硅化钛形成提供硅来防止形成微孔。 硅和砷植入物的组合非晶化效应也有助于亚微米宽多硅化物线上的硅化物相变，从而改善其导电性。

公开(公告)号：US06577926B1

公开(公告)日：2003-06-10

申请号：US09280508

申请日：1999-03-30

Applicant: Shih Hui Chang ,  Kuo-Hsien Cheng ,  Cheng Kun Lin ,  Wen Zen Chiu

Inventor： Shih Hui Chang ,  Kuo-Hsien Cheng ,  Cheng Kun Lin ,  Wen Zen Chiu

IPC: G05B2100

CPC classification number: G05B9/02

Abstract: Faults occurring in the operation of a rapid thermal process system are detected and dynamically controlled in-situ. A data set is generated which represents the power applied to heating elements which are spatially arranged in a plurality of zones. The data is converted to a sequence of fractions respectively representing the power applied to each zone relative to the total applied power. The fractions are sequentially arranged and a least squares straight line fit for the fractions is calculated. The slope of the calculated straight line fit is used in a statistical process control system to determine whether a fault has occurred, and to make appropriate corrections in process control parameters, such as the length of time the process is carried out.

Abstract translation: 在快速热处理系统的运行中发生的故障被现场检测和动态控制。 产生表示施加到空间上布置在多个区域中的加热元件的功率的数据组。 数据被转换成分数序列，分数表示施加到每个区域相对于总施加功率的功率。 计算分数，计算分数的最小二乘法直线拟合。 在统计过程控制系统中使用计算的直线拟合的斜率来确定是否发生故障，并对过程控制参数进行适当的校正，例如过程执行的时间长度。

公开(公告)号：US06358761B1

公开(公告)日：2002-03-19

申请号：US09396521

申请日：1999-09-15

Applicant: Hui-Ju Yoo ,  Szu-An Wu ,  Cheng-Kun Lin ,  Shiow-Jye Jenq

Inventor： Hui-Ju Yoo ,  Szu-An Wu ,  Cheng-Kun Lin ,  Shiow-Jye Jenq

IPC: H01L21265

CPC classification number: G01N27/041

Abstract: A method and means for detection of oxidizing contamination in acid etching baths employed to etch silicon oxide layers from silicon substrates employed in silicon integrated circuit microelectronics fabrications. There is provided a silicon substrate having within a doped region formed employing ion implantation. The silicon substrate is immersed within a buffered oxide etch (BOE) acid bath, wherein the presence of an oxidizing contaminant correlates with an increase in the resistance of the doped region upon the removal of any silicon oxide layer on the silicon surface.

Abstract translation: 用于检测酸蚀刻液中的氧化污染物的方法和装置，其用于从用于硅集成电路微电子学制造的硅衬底上蚀刻氧化硅层。 提供了在采用离子注入形成的掺杂区域内的硅衬底。 将硅衬底浸入缓冲氧化物蚀刻（BOE）酸浴中，其中氧化污染物的存在与去除硅表面上的任何氧化硅层时的掺杂区域的电阻的增加相关。

公开(公告)号：US06030863A

公开(公告)日：2000-02-29

申请号：US151952

申请日：1998-09-11

Applicant: Shou-Zen Chang ,  Chaochieh Tsai ,  Cheng Kun Lin ,  Chi Ming Yang

Inventor： Shou-Zen Chang ,  Chaochieh Tsai ,  Cheng Kun Lin ,  Chi Ming Yang

IPC: H01L21/223 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238

CPC classification number: H01L21/2236 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823835

Abstract: A method for forming salicide contacts and polycide conductive lines in integrated circuits is described which employs the ion implantation of both germanium and arsenic into polysilicon structures and into source/drain MOSFET elements is described. The method is particularly beneficial in the manufacture of sub-micron CMOS integrated circuits. Germanium is implanted into the polysilicon and into the source/drain surfaces forming a amorphized surface layer. Next a low dose, low energy arsenic implant is administered into the amorphized layer. The low dose shallow arsenic implant in concert with the amorphized layer initiates a balanced formation of titanium suicide over both NMOS and PMOS devices in CMOS integrated circuits without degradation of the PMOS devices with an accompanying reduction of gate-to-source/drain shorts. Amorphization by the electrically neutral germanium ions permits the use of a lower dose of arsenic than would be required if arsenic alone were implanted. The combined amorphization effect of the germanium and arsenic implants also facilitates a suicide phase transition on sub-micron wide polycide lines thereby improving their conductivity.

Abstract translation: 描述了在集成电路中形成硅化物接触和多硅化物导线的方法，其采用锗和砷的离子注入到多晶硅结构中并描述为源极/漏极MOSFET元件。 该方法在亚微米CMOS集成电路的制造中特别有益。 将锗植入多晶硅并进入形成非晶化表面层的源/漏表面。 接下来，将低剂量的低能量砷植入物施用于非晶化层。 与非晶化层一致的低剂量浅砷植入物在CMOS集成电路中的NMOS和PMOS器件上均衡形成钛硅化物，而不会导致PMOS器件劣化，同时伴随着栅极/源极/漏极短路的减少。 通过电中性锗离子的非晶化允许使用比单独砷植入所需要的更低剂量的砷。 锗和砷植入物的组合非晶化效应也有助于在亚微米宽的多杀线上进行自杀相变，从而提高其导电性。