公开(公告)号：US6060374A

公开(公告)日：2000-05-09

申请号：US090614

申请日：1998-06-04

Applicant: Cheng-Kun Lin ,  Szu-An Wu

Inventor： Cheng-Kun Lin ,  Szu-An Wu

IPC: H01L21/425

CPC classification number: H01L21/26506 ,  H01L21/28211 ,  H01L22/12

Abstract: Measurement of contaminating nitrogen during silicon ion implantation has been achieved by including a silicon wafer as a monitor in the implantation chamber. After silicon ion implantation, the monitor is subjected to a rapid thermal oxidation (about 1,100.degree. C. for one minute) and the thickness of the resulting grown oxide layer is measured. The thinner the oxide layer (relative to an oxide layer grown on pure silicon) the greater the degree of nitrogen contamination. For example, a reduction in oxide thickness of about 30 Angstroms corresponds to a nitrogen dosage of about 10.sup.13 atoms/sq. cm. By measuring total ion dosage during implantation and then subtracting the measured nitrogen dosage, the corrected silicon dosage may also be computed.

Abstract translation: 硅离子注入期间污染氮的测量已经通过将硅晶片作为监测器包括在注入室来实现。 在硅离子注入之后，将监测器进行快速热氧化（约1100℃1分钟），并测量所得生长的氧化物层的厚度。 氧化物层（相对于在纯硅上生长的氧化物层）越薄，氮污染程度越大。 例如，约30埃的氧化物厚度的减小对应于大约1013个原子/平方的氮剂量。 厘米。 通过测量植入期间的总离子剂量，然后减去测量的氮剂量，也可以计算校正的硅剂量。

公开(公告)号：US06358761B1

公开(公告)日：2002-03-19

申请号：US09396521

申请日：1999-09-15

Applicant: Hui-Ju Yoo ,  Szu-An Wu ,  Cheng-Kun Lin ,  Shiow-Jye Jenq

Inventor： Hui-Ju Yoo ,  Szu-An Wu ,  Cheng-Kun Lin ,  Shiow-Jye Jenq

IPC: H01L21265

CPC classification number: G01N27/041

Abstract: A method and means for detection of oxidizing contamination in acid etching baths employed to etch silicon oxide layers from silicon substrates employed in silicon integrated circuit microelectronics fabrications. There is provided a silicon substrate having within a doped region formed employing ion implantation. The silicon substrate is immersed within a buffered oxide etch (BOE) acid bath, wherein the presence of an oxidizing contaminant correlates with an increase in the resistance of the doped region upon the removal of any silicon oxide layer on the silicon surface.

Abstract translation: 用于检测酸蚀刻液中的氧化污染物的方法和装置，其用于从用于硅集成电路微电子学制造的硅衬底上蚀刻氧化硅层。 提供了在采用离子注入形成的掺杂区域内的硅衬底。 将硅衬底浸入缓冲氧化物蚀刻（BOE）酸浴中，其中氧化污染物的存在与去除硅表面上的任何氧化硅层时的掺杂区域的电阻的增加相关。

公开(公告)号：US20130149807A1

公开(公告)日：2013-06-13

申请号：US13416004

申请日：2012-03-09

Applicant: Shiu-Ko JangJian ,  Volume Chien ,  Szu-An Wu

Inventor： Shiu-Ko JangJian ,  Volume Chien ,  Szu-An Wu

IPC: H01L31/0232 ,  H01L31/02

CPC classification number: H01L27/1464 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14685 ,  H01L27/14698

Abstract: A backside illuminated CMOS image sensor comprises a photo active region formed over a substrate using a front side ion implantation process and an extended photo active region formed adjacent to the photo active region, wherein the extended photo active region is formed by using a backside ion implantation process. The backside illuminated CMOS image sensor may further comprise a laser annealed layer on the backside of the substrate. The extended photo active region helps to increase the number of photons converted into electrons so as to improve quantum efficiency.

Abstract translation: 背面照明CMOS图像传感器包括使用前侧离子注入工艺和邻近光有源区形成的延伸的光有源区在衬底上形成的光有源区，其中扩展的光有源区通过使用背侧离子注入形成 处理。 背面照明的CMOS图像传感器还可以包括在衬底的背面上的激光退火层。 扩展的光有源区域有助于增加转换成电子的光子数量，以提高量子效率。

公开(公告)号：US20130134541A1

公开(公告)日：2013-05-30

申请号：US13420279

申请日：2012-03-14

Applicant: Shih-Chieh Chang ,  Jian-Shin Tsai ,  Chih-Chang Huang ,  Ing-Ju Lee ,  Ching-Yao Sun ,  Jyun-Ru Wu ,  Ching-Che Huang ,  Szu-An Wu ,  Ying-Lang Wang

Inventor： Shih-Chieh Chang ,  Jian-Shin Tsai ,  Chih-Chang Huang ,  Ing-Ju Lee ,  Ching-Yao Sun ,  Jyun-Ru Wu ,  Ching-Che Huang ,  Szu-An Wu ,  Ying-Lang Wang

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L27/1464 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14683 ,  H01L27/14685

Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.

Abstract translation: 一种器件包括具有正面和背面的半导体衬底。 光敏器件设置在半导体衬底的表面处，其中光敏器件被配置为从半导体衬底的背面接收光信号，并将光信号转换为电信号。 在半导体衬底的背面设有非晶态粘接层。 非晶态粘合层包括氮和金属的化合物。 金属屏蔽层设置在半导体衬底的背面并与非晶态粘合层接触。

公开(公告)号：US20110070546A1

公开(公告)日：2011-03-24

申请号：US12562248

申请日：2009-09-18

Applicant: Hung-Ting Pan ,  Jing-Huan Chen ,  Wei-Chung Ma ,  Hsin-Chun Chiang ,  Po-Chung Cheng ,  Szu-An Wu

Inventor： Hung-Ting Pan ,  Jing-Huan Chen ,  Wei-Chung Ma ,  Hsin-Chun Chiang ,  Po-Chung Cheng ,  Szu-An Wu

IPC: G03F7/20

CPC classification number: G03F7/30 ,  G03F7/38 ,  H01L21/0273

Abstract: A method of lithography patterning includes coating a resist layer on a substrate; performing an exposing process to the resist layer using a lithography tool with a numerical aperture tuned between about 0.5 and about 0.6; baking the resist layer; thereafter performing a first developing process to the resist layer for a first period of time; and performing a second developing process to the resist layer for a second period of time.

Abstract translation: 光刻图案的方法包括在基板上涂覆抗蚀剂层; 使用数值孔径调节在约0.5和约0.6之间的光刻工具对抗蚀剂层进行曝光处理; 烘烤抗蚀剂层; 然后对所述抗蚀剂层进行第一显影处理第一时间; 以及对所述抗蚀剂层进行第二显影处理第二时间段。

公开(公告)号：US07611589B2

公开(公告)日：2009-11-03

申请号：US11072114

申请日：2005-03-04

Applicant: Jun Wu ,  Dong-Xuan Lu ,  Shih-Chi Lin ,  Wen-Long Lee ,  Yi-An Jian ,  Guang-Cheng Wang ,  Shiu-Ko JangJian ,  Chyi-Tsong Ni ,  Szu-An Wu ,  Ying-Lang Wang

Inventor： Jun Wu ,  Dong-Xuan Lu ,  Shih-Chi Lin ,  Wen-Long Lee ,  Yi-An Jian ,  Guang-Cheng Wang ,  Shiu-Ko JangJian ,  Chyi-Tsong Ni ,  Szu-An Wu ,  Ying-Lang Wang

IPC: B08B3/02 ,  B08B1/04

CPC classification number: B08B1/04 ,  B08B3/02 ,  H01L21/67051

Abstract: A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.

Abstract translation: 旋转晶片清洗的方法。 该方法包括控制旋转速度和垂直喷水压力。 垂直喷射压力和旋转速度基本保持成反比例。 晶圆转速在50至1200rpm之间。 垂直晶片喷射压力为0.05至100KPa。

公开(公告)号：US07349086B2

公开(公告)日：2008-03-25

申请号：US11322540

申请日：2005-12-30

Applicant: Joung-Wei Liou ,  Jacky Huang ,  Chih-Ming Ke ,  Szu-An Wu

Inventor： Joung-Wei Liou ,  Jacky Huang ,  Chih-Ming Ke ,  Szu-An Wu

IPC: G01J4/00

CPC classification number: G01N21/8422 ,  G01N21/211

Abstract: A system for measuring optical properties of a sample is provided. A light source provides incident polarized light. A detector detects reflected light from the sample surface. A processor determines a first coefficient (R) of the reflected light detected by the detector, determines a second coefficient (n), extinction coefficient (k), and thickness of the film based on the measured first coefficient, and determines a first dielectric constant (∈1) and a second dielectric constant (∈2) of the film according to the second coefficient (n) and extinction coefficient (k).

Abstract translation: 提供了一种用于测量样品的光学性质的系统。 光源提供入射偏振光。 检测器检测来自样品表面的反射光。 处理器确定由检测器检测的反射光的第一系数（R），基于测量的第一系数确定胶片的第二系数（n），消光系数（k）和厚度，并且确定第一介电常数 根据第二系数（n）和消光系数（k），薄膜的第二介电常数（εε2）和第二介电常数（ε∈2 <2）。

公开(公告)号：US20060105558A1

公开(公告)日：2006-05-18

申请号：US10992161

申请日：2004-11-18

Applicant: Harry Chuang ,  Chen-Hua Yu ,  Po-Hsiung Leu ,  Szu-An Wu

Inventor： Harry Chuang ,  Chen-Hua Yu ,  Po-Hsiung Leu ,  Szu-An Wu

IPC: H01L21/44

CPC classification number: H01L21/76801 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76835

Abstract: System and method for providing an inter-metal dielectric that prevents or reduces film delamination and contact corrosion defects is provided. A preferred embodiment comprises forming a chemical-mechanical polishing (CMP) stop layer over the surface of an inter-metal dielectric prior to forming interconnects and vias. Interconnect and vias may be formed with a dual-damascene process and filled with a conductive material. After the interconnects and vias are filled with a conductive material, a CMP process planarizes the wafer, leaving at least a portion of the CMP stop layer.

Abstract translation: 提供了用于提供防止或减少膜分层和接触腐蚀缺陷的金属间电介质的系统和方法。 优选实施例包括在形成互连和通孔之前在金属间电介质的表面上形成化学 - 机械抛光（CMP）阻挡层。 互连和通孔可以用双镶嵌工艺形成并填充有导电材料。 在互连和通孔填充导电材料之后，CMP工艺使晶片平坦化，留下至少一部分CMP停止层。

公开(公告)号：US06479098B1

公开(公告)日：2002-11-12

申请号：US09747135

申请日：2000-12-26

Applicant: Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

Inventor： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

IPC: C23C1640

CPC classification number: H01J37/32477 ,  C23C16/4404 ,  Y10T428/2495 ,  Y10T428/265

Abstract: A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.

Abstract translation: 一种用于减少具有室等离子体处理区域部件的处理室10中的污染物的方法，包括以下步骤。 腔室等离子体处理区域部件被清洁。 然后如下调节室。 在室等离子体处理区域部件上形成第一USG层。 在第一USG层上形成FSG层。 在FSG层上形成第二个USG层。 其中USG，FSG和第二USG层包括UFU季电影。 UFU季涂膜处理室的室等离子体处理区域部件包括：室上的内部USG层等离子体处理区域部件; 内部USG层上的FSG层; 以及FSG层上的外部USG层。

公开(公告)号：US06436791B1

公开(公告)日：2002-08-20

申请号：US09880259

申请日：2001-06-14

Applicant: Shih-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang ,  Guey-Bao Huang

Inventor： Shih-Chi Lin ,  Szu-An Wu ,  Ying-Lang Wang ,  Guey-Bao Huang

IPC: H01L21302

CPC classification number: H01L21/76224

Abstract: A method of forming a shallow trench isolation structure comprising the following steps. A substrate having an upper surface is provided. A pad oxide layer is formed upon the substrate. A nitride layer is formed over the pad oxide layer. The nitride layer having an upper surface. A trench is formed by etching the nitride layer, pad oxide layer and a portion of the substrate. The trench having a bottom and side walls. An oxide film is deposited upon the etched nitride layer surface, and the bottom and side walls of trench. The oxide film is removed from over the etched nitride layer surface, and the bottom of the trench to expose a portion of substrate within the trench. The removal of oxide film leaving oxide spacers over the trench side walls. Epitaxial silicon is selectively deposited over the exposed portion of substrate, filling the trench. A thermal oxide layer is formed over the epitaxial silicon, annealing the interface between the epitaxial silicon and the oxide spacers. The etched nitride layer and the oxide layer from over the etched substrate; and a portion of the oxide spacers extending above the surface of the etched substrate are removed, whereby the shallow trench isolation structure is formed within the trench.

Abstract translation: 一种形成浅沟槽隔离结构的方法，包括以下步骤。 提供具有上表面的基板。 衬底氧化层形成在衬底上。 在衬垫氧化物层上形成氮化物层。 氮化物层具有上表面。 通过蚀刻氮化物层，衬垫氧化物层和衬底的一部分来形成沟槽。 沟槽具有底部和侧壁。 在蚀刻的氮化物层表面和沟槽的底部和侧壁上沉积氧化物膜。 从蚀刻的氮化物层表面上方的氧化膜和沟槽的底部去除氧化膜，以露出沟槽内的衬底的一部分。 去除在沟槽侧壁上留下氧化物间隔物的氧化物膜。 外延硅被选择性地沉积在衬底的暴露部分上，填充沟槽。 在外延硅上形成热氧化层，退火外延硅与氧化物间隔物之间​​的界面。 蚀刻的氮化物层和来自蚀刻的衬底上的氧化物层; 并且去除在蚀刻的衬底的表面上方延伸的氧化物间隔物的一部分，由此在沟槽内形成浅沟槽隔离结构。