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    ESD Protection Devices
    2.
    发明申请
    ESD Protection Devices 审中-公开
    ESD保护装置

    公开(公告)号：US20110215372A1

    公开(公告)日：2011-09-08

    申请号：US13093589

    申请日：2011-04-25

    Applicant: Chien-Hui Chuang

    Inventor： Chien-Hui Chuang

    IPC: H01L27/08

    CPC classification number: H01L27/0259 ,  H01L29/0692 ,  H01L29/7436 ,  H01L29/749

    Abstract: An ESD protection device is provided. The ESD protection device comprises an SCR and an ESD detection circuit. The SCR is coupled between a high voltage and a ground and has a special semiconductor structure which saves area. When the ESD detection circuit detects an ESD event, the ESD detection circuit drives the SCR to provide a discharging path.

    Abstract translation: 提供ESD保护装置。 ESD保护装置包括SCR和ESD检测电路。 SCR耦合在高电压和地之间，并具有节省面积的特殊半导体结构。 当ESD检测电路检测到ESD事件时，ESD检测电路驱动SCR以提供放电路径。

    ESD protection devices
    3.
    发明授权
    ESD protection devices 有权
    ESD保护装置

    公开(公告)号：US07956418B2

    公开(公告)日：2011-06-07

    申请号：US12125241

    申请日：2008-05-22

    Applicant: Chien-Hui Chuang

    Inventor： Chien-Hui Chuang

    IPC: H01L23/60

    CPC classification number: H01L27/0259 ,  H01L29/0692 ,  H01L29/7436 ,  H01L29/749

    Abstract: An ESD protection device is provided. The ESD protection device comprises an SCR and an ESD detection circuit. The SCR is coupled between a high voltage and a ground and has a special semiconductor structure which saves area. When the ESD detection circuit detects an ESD event, the ESD detection circuit drives the SCR to provide a discharging path.

    Abstract translation: 提供ESD保护装置。 ESD保护装置包括SCR和ESD检测电路。 SCR耦合在高电压和地之间，并具有节省面积的特殊半导体结构。 当ESD检测电路检测到ESD事件时，ESD检测电路驱动SCR以提供放电路径。

    Pre-buffer level shifter and input/output buffer apparatus
    4.
    发明授权
    Pre-buffer level shifter and input/output buffer apparatus 失效
    预缓冲电平移位器和输入/输出缓冲装置

    公开(公告)号：US07282953B2

    公开(公告)日：2007-10-16

    申请号：US11223742

    申请日：2005-09-08

    Applicant: Chih-Hung Wu ,  Meng-Jer Wey ,  Chien-Hui Chuang

    Inventor： Chih-Hung Wu ,  Meng-Jer Wey ,  Chien-Hui Chuang

    IPC: H03K19/0175 ,  H03K19/094

    CPC classification number: H03K3/356 ,  H03K19/018507 ,  H03K19/018521

    Abstract: A pre-buffer level shifter and an I/O buffer apparatus are provided. The pre-buffer level shifter includes a switchable current source, a current mirror, a buffer unit, a first clamping circuit and a second clamping circuit. Because of a clamping circuit inside a thin oxide MOS transistor device of the pre-buffer level shifter, the present invention can control the voltage swing of the signal for driving an output buffer within a suitable voltage range. Thus, the pre-buffer level shifter can correctly drive the output buffer made of thin oxide MOS transistor devices, increase the operating speed and ensure the reliability thereof.

    Abstract translation: 提供了预缓冲器电平移位器和I / O缓冲装置。 预缓冲电平移位器包括可切换电流源，电流镜，缓冲单元，第一钳位电路和第二钳位电路。 由于在预缓冲器电平移位器的薄氧化物MOS晶体管器件内部存在钳位电路，本发明可以控制用于驱动输出缓冲器的信号在合适的电压范围内的电压摆幅。 因此，预缓冲电平移位器可以正确地驱动由薄氧化物MOS晶体管器件制成的输出缓冲器，提高工作速度并确保其可靠性。

    Poly fuse trimming circuit
    5.
    发明申请
    Poly fuse trimming circuit 失效
    聚熔丝修整电路

    公开(公告)号：US20070152733A1

    公开(公告)日：2007-07-05

    申请号：US11324980

    申请日：2006-01-03

    Applicant: Jia-Jio Huang ,  Chien-Hui Chuang

    Inventor： Jia-Jio Huang ,  Chien-Hui Chuang

    IPC: H01H37/76

    CPC classification number: G11C17/18

    Abstract: A poly fuse trimming circuit. The poly fuse trimming circuit comprises a poly fuse and a silicon controlled rectifier (SCR) device. The poly fuse is coupled between a first fixed potential and an output node. The SCR device is controlled by a trimming signal and has an anode coupled to the output node and a cathode coupled to a second fixed potential.

    Abstract translation: 多熔丝修整电路。 多熔丝修整电路包括多晶硅熔丝和可控硅整流器（SCR）器件。 多晶硅熔丝耦合在第一固定电位和输出节点之间。 SCR器件由修整信号控制，并且具有耦合到输出节点的阳极和耦合到第二固定电位的阴极。

    Pre-buffer level shifter and input/output buffer apparatus
    6.
    发明申请
    Pre-buffer level shifter and input/output buffer apparatus 失效

    公开(公告)号：US20070052445A1

    公开(公告)日：2007-03-08

    申请号：US11223742

    申请日：2005-09-08

    Applicant: Chih-Hung Wu ,  Meng-Jer Wey ,  Chien-Hui Chuang

    Inventor： Chih-Hung Wu ,  Meng-Jer Wey ,  Chien-Hui Chuang

    IPC: H03K19/0175

    CPC classification number: H03K3/356 ,  H03K19/018507 ,  H03K19/018521

    Abstract: A pre-buffer level shifter and an I/O buffer apparatus are provided. The pre-buffer level shifter includes a switchable current source, a current mirror, a buffer unit, a first clamping circuit and a second clamping circuit. Because of a clamping circuit inside a thin oxide MOS transistor device of the pre-buffer level shifter, the present invention can control the voltage swing of the signal for driving an output buffer within a suitable voltage range. Thus, the pre-buffer level shifter can correctly drive the output buffer made of thin oxide MOS transistor devices, increase the operating speed and ensure the reliability thereof.

    DRIVER IMPEDANCE CONTROL APPARATUS AND SYSTEM
    7.
    发明申请
    DRIVER IMPEDANCE CONTROL APPARATUS AND SYSTEM 有权
    驱动阻抗控制装置和系统

    公开(公告)号：US20070057692A1

    公开(公告)日：2007-03-15

    申请号：US11162531

    申请日：2005-09-14

    Applicant: Chien-Hui Chuang ,  Ren-Jeng Chiang ,  Ih-Hwa Chang

    Inventor： Chien-Hui Chuang ,  Ren-Jeng Chiang ,  Ih-Hwa Chang

    IPC: H03K19/003

    CPC classification number: H03K19/0005

    Abstract: A driver impedance control apparatus and system for determining the impedance of at least one driver are provided. The driver impedance control apparatus includes a first reference impedance, a second reference impedance, a dummy pull-up array, a dummy pull-down array, a pull-up array control unit and a pull-down array control unit. The pull-up array control unit controls the pull-up impedance of the driver by detecting a voltage from a first voltage divide point between the first reference impedance and the dummy pull-up array. The pull-down array control unit controls the pull-down impedance of the driver by detecting a voltage from a second voltage divide point between the second reference impedance and the dummy pull-down array.

    Abstract translation: 提供了用于确定至少一个驱动器的阻抗的驱动器阻抗控制装置和系统。 驱动器阻抗控制装置包括第一参考阻抗，第二参考阻抗，虚拟上拉阵列，虚拟下拉阵列，上拉阵列控制单元和下拉阵列控制单元。 上拉阵列控制单元通过检测来自第一参考阻抗和虚拟上拉阵列之间的第一分压点的电压来控制驱动器的上拉阻抗。 下拉阵列控制单元通过检测来自第二参考阻抗和虚拟下拉阵列之间的第二分压点的电压来控制驱动器的下拉阻抗。

    Power-rail electrostatic discharge protection circuit with a dual trigger design
    8.
    发明授权
    Power-rail electrostatic discharge protection circuit with a dual trigger design 有权
    电源轨静电放电保护电路采用双触发设计

    公开(公告)号：US06728086B2

    公开(公告)日：2004-04-27

    申请号：US10050018

    申请日：2002-01-15

    Applicant: Kei-Kang Hung ,  Chien-Hui Chuang

    Inventor： Kei-Kang Hung ,  Chien-Hui Chuang

    IPC: H02H900

    CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A power-rail ESD (electrostatic discharge) protection circuit with a dual trigger design is proposed, which is coupled between a first power line and a second power line connected to an IC device for protecting the IC device against ESD on the first power line and the second power line. The proposed power-rail ESD protection circuit comprises a control circuit and at least one MOS device. The control circuit is coupled between the first power line and the second power line, and which is capable of, in the event of ESD in the first power line and the second power line, being triggered by the ESD to output a substrate-triggering voltage and a gate-driving voltage to the MOS device, causing the MOS device to bypass the ESD current from the first power line and the second power line. The circuit configuration of the proposed power-rail ESD protection circuit can help reduce the junction breakdown voltage in a MOS device and increase in ESD robustness.

    Abstract translation: 提出了具有双触发设计的电力轨道ESD（静电放电）保护电路，其耦合在连接到IC装置的第一电力线和第二电力线之间，用于保护IC装置免受第一电力线上的ESD， 第二条电力线。 所提出的电源轨ESD保护电路包括控制电路和至少一个MOS器件。 控制电路耦合在第一电力线和第二电力线之间，并且其能够在第一电力线和第二电力线中的ESD的情况下被ESD触发以输出基板触发电压 以及向MOS器件施加栅极驱动电压，使MOS器件从第一电力线和第二电力线旁路ESD电流。 所提出的电力轨道ESD保护电路的电路配置有助于降低MOS器件中的结击穿电压，增加ESD稳定性。

    Electrostatic discharge protection circuit for protecting input and output buffer
    9.
    发明授权
    Electrostatic discharge protection circuit for protecting input and output buffer 失效
    用于保护输入和输出缓冲器的静电放电保护电路

    公开(公告)号：US06639772B2

    公开(公告)日：2003-10-28

    申请号：US10041237

    申请日：2002-01-07

    Applicant: Chien-Hui Chuang ,  Kei-Kang Hung

    Inventor： Chien-Hui Chuang ,  Kei-Kang Hung

    IPC: H02H300

    CPC classification number: H01L27/0277

    Abstract: An electrostatic discharge (ESD) protection circuit for protecting input and output buffers. The ESD protection circuit is driven by a first voltage source and a second voltage source and coupled to a bonding pad. The ESD protection circuit has a first resistor, a first PMOS transistor, a first NMOS transistor, a first diode series, a second PMOS transistor, a second resistor, a third PMOS transistor, a second NMOS transistor, a second diode series and a third NMOS transistor. The electrical devices combine to form different types of ESD protection circuits, each capable of protecting the input buffer or output buffer against the damaging effects of an electrostatic discharge.

    Abstract translation: 一种用于保护输入和输出缓冲器的静电放电（ESD）保护电路。 ESD保护电路由第一电压源和第二电压源驱动并耦合到接合焊盘。 ESD保护电路具有第一电阻器，第一PMOS晶体管，第一NMOS晶体管，第一二极管系列，第二PMOS晶体管，第二电阻器，第三PMOS晶体管，第二NMOS晶体管，第二二极管串联和第三 NMOS晶体管。 电气设备组合形成不同类型的ESD保护电路，每个ESD保护电路能够保护输入缓冲器或输出缓冲器免受静电放电的破坏作用。

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