公开(公告)号：US11501350B2

公开(公告)日：2022-11-15

申请号：US16339720

申请日：2018-12-24

Applicant: Seok-Ho Bae ,  Han-Jun Bae ,  Hyun-Woong Bae

Inventor： Seok-Ho Bae ,  Han-Jun Bae ,  Hyun-Woong Bae

IPC: G06Q30/00 ,  G06Q30/06 ,  G06F16/28 ,  G06F16/953

Abstract: An intermediary device for mediating a transaction of used heavy equipment may be provided. The intermediary device may provide a semitransparent photographing guideline including guidance on a photographing portion and a photographing angle for photographing a heavy equipment image on a heavy equipment portion basis to a sale terminal device. When the intermediary device receives heavy equipment sales request information including at least one of a nameplate image and a registration certificate image of the heavy equipment to be sold, an appearance image, first heavy equipment information, heavy equipment location information, and a desired sale price from the sale terminal device, the intermediary device may recognize at least one of the nameplate image and the registration certificate image to extract second heavy equipment information. The intermediary device may compare the first heavy equipment information with the second heavy equipment information to authenticate the first heavy equipment information, and calculate an estimated sale price in which a commission and a tax are added to the desired sale price when the first heavy equipment information is successfully authenticated.

公开(公告)号：US08618637B2

公开(公告)日：2013-12-31

申请号：US12192173

申请日：2008-08-15

Applicant: Han Jun Bae ,  Woong Sun Lee

Inventor： Han Jun Bae ,  Woong Sun Lee

IPC: H01L23/488

CPC classification number: H01L23/53276 ,  H01L23/3128 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads. Through-electrodes are formed in the semiconductor chip and are electrically connected to the bonding pads. The through electrodes comprise a plurality of conductors and a plurality of voids that are defined by the conductors. Each conductor may include a plurality of nanowires grouped into a spherical shape having a plurality of voids, a plurality of nanowires grouped into a polygonal shape having a plurality of voids, or the conductors may include a plurality of micro solder balls. The voids of the through electrode absorb stress caused when head is generated during the driving of the semiconductor package.

Abstract translation: 半导体封装包括具有多个焊盘的半导体芯片。 在半导体芯片中形成贯通电极，与导体焊盘电连接。 贯通电极包括由导体限定的多个导体和多个空隙。 每个导体可以包括分组成具有多个空隙的球形的多个纳米线，多个纳米线分组成具有多个空隙的多边形，或者导体可以包括多个微焊球。 通过电极的空隙吸收在半导体封装的驱动期间产生磁头时引起的应力。

公开(公告)号：US08072046B2

公开(公告)日：2011-12-06

申请号：US12209584

申请日：2008-09-12

Applicant: Han Jun Bae ,  Jong Hoon Kim

Inventor： Han Jun Bae ,  Jong Hoon Kim

IPC: H01L23/538 ,  H05K1/02

CPC classification number: H05K3/4046 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K2201/0347 ,  H05K2201/10242 ,  H01L2924/00

Abstract: A stacked semiconductor package includes a first semiconductor package having a first semiconductor chip having a first pad and a through-hole passing through a the portion corresponding to the pad; a second semiconductor package disposed over the first semiconductor package, and including a second semiconductor chip having a second pad disposed at a portion corresponding to the first pad and blocking the through-hole; and a through-electrode disposed within the through-hole, and having a pillar shaped core supported by the second pad, a through-electrode unit disposed over a surface of the core and electrically connected with the second pad, a first metal layer interposed between the core and the through electrode unit, and a second metal layer interposed between an inner surface of the first semiconductor chip formed by the through-hole and the through-electrode unit.

Abstract translation: 堆叠半导体封装包括具有第一半导体芯片的第一半导体封装，第一半导体芯片具有第一焊盘和穿过对应于焊盘的部分的通孔; 第二半导体封装，设置在所述第一半导体封装上，并且包括第二半导体芯片，所述第二半导体芯片具有设置在与所述第一焊盘对应的部分处并阻塞所述通孔的第二焊盘; 以及设置在所述通孔内的贯通电极，并具有由所述第二焊盘支撑的柱状芯，贯通电极单元，设置在所述芯的表面上并与所述第二焊盘电连接;第一金属层， 芯和贯通电极单元，以及插入在由通孔形成的第一半导体芯片的内表面和通孔单元之间的第二金属层。

公开(公告)号：US20090261458A1

公开(公告)日：2009-10-22

申请号：US12209584

申请日：2008-09-12

Applicant: Han Jun BAE ,  Jong Hoon KIM

Inventor： Han Jun BAE ,  Jong Hoon KIM

IPC: H01L23/538 ,  H05K1/02

CPC classification number: H05K3/4046 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K2201/0347 ,  H05K2201/10242 ,  H01L2924/00

Abstract: A stacked semiconductor package includes a first semiconductor package having a first semiconductor chip having a first pad and a through-hole passing through a the portion corresponding to the pad; a second semiconductor package disposed over the first semiconductor package, and including a second semiconductor chip having a second pad disposed at a portion corresponding to the first pad and blocking the through-hole; and a through-electrode disposed within the through-hole, and having a pillar shaped core supported by the second pad, a through-electrode unit disposed over a surface of the core and electrically connected with the second pad, a first metal layer interposed between the core and the through electrode unit, and a second metal layer interposed between an inner surface of the first semiconductor chip formed by the through-hole and the through-electrode unit.

Abstract translation: 堆叠半导体封装包括具有第一半导体芯片的第一半导体封装，第一半导体芯片具有第一焊盘和穿过对应于焊盘的部分的通孔; 第二半导体封装，设置在所述第一半导体封装上，并且包括第二半导体芯片，所述第二半导体芯片具有设置在与所述第一焊盘对应的部分处并阻塞所述通孔的第二焊盘; 以及设置在所述通孔内的贯通电极，并具有由所述第二焊盘支撑的柱状芯，贯通电极单元，设置在所述芯的表面上并与所述第二焊盘电连接;第一金属层， 芯和贯通电极单元，以及插入在由通孔形成的第一半导体芯片的内表面和通孔单元之间的第二金属层。

公开(公告)号：US20090321892A1

公开(公告)日：2009-12-31

申请号：US12192173

申请日：2008-08-15

Applicant: Han Jun BAE ,  Woong Sun LEE

Inventor： Han Jun BAE ,  Woong Sun LEE

IPC: H01L23/488

CPC classification number: H01L23/53276 ,  H01L23/3128 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads. Through-electrodes are formed in the semiconductor chip and are electrically connected to the bonding pads. The through electrodes comprise a plurality of conductors and a plurality of voids that are defined by the conductors. Each conductor may include a plurality of nanowires grouped into a spherical shape having a plurality of voids, a plurality of nanowires grouped into a polygonal shape having a plurality of voids, or the conductors may include a plurality of micro solder balls. The voids of the through electrode absorb stress caused when head is generated during the driving of the semiconductor package.

Abstract translation: 半导体封装包括具有多个焊盘的半导体芯片。 在半导体芯片中形成贯通电极，与导体焊盘电连接。 贯通电极包括由导体限定的多个导体和多个空隙。 每个导体可以包括分组成具有多个空隙的球形的多个纳米线，多个纳米线分组成具有多个空隙的多边形，或者导体可以包括多个微焊球。 通过电极的空隙吸收在半导体封装的驱动期间产生磁头时引起的应力。

公开(公告)号：US20080116563A1

公开(公告)日：2008-05-22

申请号：US11754492

申请日：2007-05-29

Applicant: Han Jun Bae ,  Jae Myun Kim

Inventor： Han Jun Bae ,  Jae Myun Kim

IPC: H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor package includes a substrate having a plurality of connection pads and a plurality of ball lands; a semiconductor chip attached to one surface of the substrate and having a plurality of bonding pads that are connected to the respective connection pads of the substrate; a first molding structure covering an upper surface of the substrate including a connection region between the bonding pads and the connection pads and the semiconductor chip; a second molding structure formed adjacent to an edge of the lower surface of the substrate; and a plurality of solder balls attached to the respective ball lands of the substrate.

Abstract translation: 半导体封装包括具有多个连接焊盘和多个焊盘的衬底; 半导体芯片，其附接到所述基板的一个表面，并且具有连接到所述基板的各个连接焊盘的多个焊盘; 覆盖所述基板的上表面的第一模制结构，包括所述焊盘与所述连接焊盘和所述半导体芯片之间的连接区域; 与所述基板的下表面的边缘相邻形成的第二模制结构; 以及附接到基板的相应球台的多个焊球。

公开(公告)号：US20210334869A1

公开(公告)日：2021-10-28

申请号：US16339720

申请日：2018-12-24

Applicant: Seok-Ho BAE ,  Han-Jun BAE ,  Hyun-Woong BAE

Inventor： Seok-Ho BAE ,  Han-Jun BAE ,  Hyun-Woong BAE

IPC: G06Q30/06 ,  G06F16/28 ,  G06F16/953

Abstract: An intermediary device for mediating a transaction of used heavy equipment may be provided. The intermediary device may provide a semitransparent photographing guideline including guidance on a photographing portion and a photographing angle for photographing a heavy equipment image on a heavy equipment portion basis to a sale terminal device. When the intermediary device receives heavy equipment sales request information including at least one of a nameplate image and a registration certificate image of the heavy equipment to be sold, an appearance image, first heavy equipment information, heavy equipment location information, and a desired sale price from the sale terminal device, the intermediary device may recognize at least one of the nameplate image and the registration certificate image to extract second heavy equipment information. The intermediary device may compare the first heavy equipment information with the second heavy equipment information to authenticate the first heavy equipment information, and calculate an estimated sale price in which a commission and a tax are added to the desired sale price when the first heavy equipment information is successfully authenticated.

公开(公告)号：US07759807B2

公开(公告)日：2010-07-20

申请号：US11754492

申请日：2007-05-29

Applicant: Han Jun Bae ,  Jae Myun Kim

Inventor： Han Jun Bae ,  Jae Myun Kim

IPC: H01L23/29 ,  H01L21/50

CPC classification number: H01L23/3114 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor package includes a substrate having a plurality of connection pads and a plurality of ball lands; a semiconductor chip attached to one surface of the substrate and having a plurality of bonding pads that are connected to the respective connection pads of the substrate; a first molding structure covering an upper surface of the substrate including a connection region between the bonding pads and the connection pads and the semiconductor chip; a second molding structure formed adjacent to an edge of the lower surface of the substrate; and a plurality of solder balls attached to the respective ball lands of the substrate.

Abstract translation: 半导体封装包括具有多个连接焊盘和多个焊盘的衬底; 半导体芯片，其附接到所述基板的一个表面，并且具有连接到所述基板的各个连接焊盘的多个焊盘; 覆盖所述基板的上表面的第一模制结构，包括所述焊盘与所述连接焊盘和所述半导体芯片之间的连接区域; 与所述基板的下表面的边缘相邻形成的第二模制结构; 以及附接到基板的相应球台的多个焊球。