公开(公告)号：US20020166980A1

公开(公告)日：2002-11-14

申请号：US10184939

申请日：2002-07-01

Applicant: MATSUSHITA ELECTRONICS CORPORATION

Inventor： Masahiko Niwayama ,  Hiroko Kubo ,  Kenji Yoneda

IPC: H01J037/08

CPC classification number: H01L21/265 ,  H01J37/3171 ,  H01J2237/004 ,  H01J2237/31701 ,  H01L21/26513

Abstract: An impurity introducing apparatus of the present invention includes: a system for introducing an impurity having charges into a target to be processed, the target being a semiconductor substrate or a film formed on the substrate; a system for supplying electrons into the target, the electrons canceling the charges of the impurity; and a system for controlling the maximum energy of the electrons supplied by the electron supply system at a predetermined value or less.

Abstract translation: 本发明的杂质导入装置包括：将具有电荷的杂质引入被处理对象物，所述靶为半导体基板或形成在所述基板上的膜的系统; 用于向目标物质供给电子的系统，电子消除杂质的电荷; 以及用于控制由电子供给系统提供的电子的最大能量以预定值或更小的系统。

公开(公告)号：US20020160552A1

公开(公告)日：2002-10-31

申请号：US10164616

申请日：2002-06-10

Applicant: Matsushita Electronics Corporation

Inventor： Masanori Minamio ,  Osamu Adachi ,  Toru Nomura

IPC: H01L021/44

CPC classification number: H01L21/4832 ,  H01L21/4842 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2221/68377 ,  H01L2224/16245 ,  H01L2224/32014 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/207

Abstract: A terminal land frame includes a frame body and a plurality of lands. Each of these lands is formed out of the frame body to be connected to the frame body via a thinned portion and protrude therefrom. When the lands are pressed in a direction in which the lands protrude from the frame body, the thinned portions are fractured and the lands are easily separable from the frame body. A semiconductor chip is mounted on some of the lands of the terminal land frame, and the chip, wires and so on, are single-side-molded with a resin encapsulant. Thereafter, when the lands are pressed on the bottom, the lands are separated from the frame body. As a result, a structure, in which the lower part of each of these lands protrudes downward from the lower surface of the resin encapsulant, is obtained, and that protruding portion is used as an external electrode. In this manner, a downsized and thinned resin-molded semiconductor device is provided at a lower cost and with higher reliability.

Abstract translation: 端子台框架包括框体和多个平台。 这些平台中的每一个由框架体形成，以经由薄的部分连接到框架体并从其突出。 当焊盘沿框架从框架体突出的方向被按压时，变薄部分断裂，并且焊盘容易与框架体分离。 半导体芯片安装在端子台架框架的一些焊盘上，芯片，电线等用树脂密封剂单面成型。 此后，当在底部上压平焊盘时，焊盘与框架体分离。 结果，得到这些区域的下部从树脂密封剂的下表面向下突出的结构，并且该突出部分被用作外部电极。 以这种方式，以更低的成本和更高的可靠性提供了一种尺寸减小和变薄的树脂模制的半导体器件。

公开(公告)号：US20020047207A1

公开(公告)日：2002-04-25

申请号：US09986289

申请日：2001-11-08

Applicant: MATSUSHITA ELECTRONICS CORPORATION

Inventor： Mitsuru Sekiguchi

IPC: H01L021/4763

CPC classification number: H01L21/76885 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A lower carbon film as a provisional film, a lower SiO2 film and an upper carbon film are formed, and then trenches having a wiring pattern are formed in the upper carbon film. Next, contact holes are formed through the lower carbon film and the lower SiO2 film. Then, wires and plugs are formed by filling in the trenches and contact holes with a barrier metal film and a Cu alloy film. After these process steps are repeatedly performed several times, a dummy opening is formed to extend downward through the uppermost SiO2 film. Thereafter, the carbon films are removed by performing ashing with oxygen introduced through the dummy opening. As a result, gas layers are formed to surround the wires and plugs. In this manner, a highly reliable gas-dielectric interconnect structure can be obtained by performing simple process steps.

Abstract translation: 形成作为临时膜的低碳膜，下部SiO 2膜和上部碳膜，然后在上部碳膜中形成具有布线图案的沟槽。 接下来，通过下部碳膜和下部SiO 2膜形成接触孔。 然后，通过用阻挡金属膜和Cu合金膜填充沟槽和接触孔来形成电线和插头。 在这些处理步骤重复进行几次之后，形成虚拟开口以向下延伸通过最上面的SiO 2膜。 此后，通过经由虚拟开口引入的氧进行灰化除去碳膜。 结果，形成气体层以包围电线和插头。 以这种方式，通过执行简单的工艺步骤可以获得高度可靠的气体 - 电介质互连结构。

公开(公告)号：US20010040253A1

公开(公告)日：2001-11-15

申请号：US09791774

申请日：2001-02-26

Applicant: Matsushita Electronics Corporation

Inventor： Kazuo Sato

IPC: H01L029/788

CPC classification number: H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

Abstract: A gate insulating film composed of silicon oxide and a floating gate electrode composed of polysilicon are formed sequentially on a P-type silicon substrate. A capacitance insulating film composed of silicon oxide and a control gate electrode composed of polysilicon are formed on the floating gate electrode. First spacer films, each composed of silicon oxide and formed over the respective side faces of individual components, and second spacer films, each composed of silicon nitride and formed on the respective first spacer films, are also provided. Even when a high-temperature heat treatment is performed in an oxidizing atmosphere, oxygen is prevented from being supplied to both end portions of the capacitance insulating film and the control gate electrode, which suppresses an increase in thickness of the capacitance insulating film at both end portions thereof.

Abstract translation: 在P型硅衬底上依次形成由氧化硅构成的栅绝缘膜和由多晶硅构成的浮栅。 在浮栅上形成由氧化硅构成的电容绝缘膜和由多晶硅构成的控制栅电极。 还提供了每个由氧化硅构成并形成在各个部件的相应侧面上的第一间隔膜和由氮化硅构成并形成在各自的第一间隔膜上的第二间隔膜。 即使在氧化气氛中进行高温热处理的情况下，也可以防止向电容绝缘膜和控制栅电极的两端部供给氧，从而抑制两端的电容绝缘膜的厚度增加 部分。

公开(公告)号：US20010031505A1

公开(公告)日：2001-10-18

申请号：US09860386

申请日：2001-05-19

Applicant: Symetrix Corporation and Matsushita Electronics Corporation

Inventor： Koji Arita ,  Shinichiro Hayashi ,  Joseph D. Cuchiaro ,  Carlos A. Paz de Araujo

IPC: H01L021/00 ,  H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119 ,  H01L021/8242

CPC classification number: H01L21/31691 ,  H01L27/10852

Abstract: A liquid precursor for forming a thin film of ferroelectric metal oxide in an integrated circuit contains metal oxides in excess of the stoichiometrically balanced amount. When the precursor comprises strontium, bismuth, tantalum and niobium for forming strontium bismuth tantalum niobate, the precursor contains excess amounts of at least one of tantalum and niobium. Capacitors containing thin films of layered superlattice material made from a precursor containing excess tantalum and niobium show good polarizability and low percentage imprint after 1010 negative polarization switching pulses at 75null C., and after 109 negative polarization switching pulses at 125null C.

公开(公告)号：US20010028588A1

公开(公告)日：2001-10-11

申请号：US09875960

申请日：2001-06-08

Applicant: MATSUSHITA ELECTRONICS CORPORATION

Inventor： Toshio Yamada ,  Akinori Shibayama

IPC: G11C007/14

CPC classification number: G11C29/785 ,  G11C7/062 ,  G11C7/14 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4099 ,  H01L27/10808

Abstract: A plurality of information memory cells and a single reference memory cell are coupled to a single word line. The reference memory cell stores reference information equivalent to a reference potential to information readout. Pieces of information, stored in the information memory cells, are fed, over respective bit lines, to first input terminals of sense amplifiers. The reference information, stored in the reference memory cell, is fed, over a bit line, to second input terminals of the sense amplifiers. When the potential of signal charges stored in the information memory cells falls due to leakage current, the potential of a signal charge stored in the reference memory cell correspondingly falls due to leakage current. This prolongs a length of time taken for a difference between these potentials to reach a sense limit, thereby achieving a longer data retention time. As a result of such arrangement, even when there occurs a small current leakage from memory cells, it is possible to secure a long data retention time thereby making it possible to obtain a long refresh cycle period.

Abstract translation: 多个信息存储单元和单个参考存储单元耦合到单个字线。 参考存储单元存储与参考电位等同于信息读出的参考信息。 存储在信息存储单元中的信息块通过各自的位线被馈送到读出放大器的第一输入端。 存储在参考存储单元中的参考信息通过位线被馈送到读出放大器的第二输入端。 当存储在信息存储单元中的信号电荷的电位由于泄漏电流而下降时，存储在参考存储单元中的信号电荷的电位由于泄漏电流而相应地下降。 这延长了这些电位之间的差异达到感测极限所需的时间长度，从而实现更长的数据保留时间。 作为这种安排的结果，即使当从存储器单元发生小的电流泄漏时，也可以确保长的数据保持时间，从而可以获得长的刷新周期。

公开(公告)号：US20010028056A1

公开(公告)日：2001-10-11

申请号：US09820309

申请日：2001-03-29

Applicant: MATSUSHITA ELECTRONICS CORPORATION

Inventor： Masaharu Yamamoto

IPC: H01L023/58

CPC classification number: H01L22/34 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To provide a method for evaluating chargeup damage caused in the practical fabrication process. Evaluation is carried out based on the electric current flowing between the source and the drain of a MOS transistor of a semiconductor element (1-1) having a wiring layer provided with an antenna effect by installing the semiconductor element (1-1) in the periphery of a practical device installed in a semiconductor substrate and measuring the electric current without attaching a probe to the gate of the semiconductor element (1-1).

Abstract translation: 提供一种用于评估在实际制造过程中引起的电荷损失的方法。 基于通过将半导体元件（1-1）安装在具有天线效应的布线层的半导体元件（1-1）的MOS晶体管的源极和漏极之间流动的电流进行评估 安装在半导体衬底中的实际装置的周边，并且测量电流而不将探针附接到半导体元件（1-1）的栅极。

公开(公告)号：US20010020709A1

公开(公告)日：2001-09-13

申请号：US09797987

申请日：2001-03-05

Applicant: Matsushita Electronics Corporation

Inventor： Keisaku Nakao ,  Akihiro Matsuda ,  Yasufumi Izutsu ,  Toyoji Ito ,  Takumi Mikawa ,  Toru Nasu ,  Yoshihisa Nagano ,  Keisuke Tanaka ,  Toshie Kutsunai

IPC: H01L029/92 ,  H01L027/108

CPC classification number: H01L28/55

Abstract: The semiconductor device of the invention includes a capacitor device, which is formed on a substrate and which includes a capacitive lower electrode, a capacitive insulating film made of an insulating metal oxide film and a capacitive upper electrode. An interlevel insulating film having an opening reaching the capacitive upper electrode is formed over the capacitor device. A metal interconnection including a titanium film is formed over the interlevel insulating film so as to be electrically connected to the capacitive upper electrode through the opening. An anti-diffusion film having conductivity is formed between the capacitive upper electrode and the metal interconnection for preventing titanium atoms composing the titanium film of the metal interconnection from passing through the capacitive upper electrode and diffusing into the capacitive insulating film.

Abstract translation: 本发明的半导体器件包括形成在基板上的电容器器件，其包括电容式下电极，由绝缘金属氧化物膜制成的电容绝缘膜和电容上电极。 在电容器装置上形成具有到达电容上电极的开口的层间绝缘膜。 在层间绝缘膜上形成包括钛膜的金属互连，以便通过开口与电容上电极电连接。 在电容上电极和金属互连之间形成具有导电性的防扩散膜，以防止构成金属互连的钛膜的钛原子通过电容上电极并扩散到电容绝缘膜。

公开(公告)号：US20010011598A1

公开(公告)日：2001-08-09

申请号：US09834153

申请日：2001-04-12

Applicant: Matsushita Electronics Corporation

Inventor： Takeshi Kobayashi ,  Hideki Fukazawa ,  Satoshi Utsunomiya

IPC: H05K005/06 ,  H01L023/28 ,  H01L023/02

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/181 ,  H05K3/3426 ,  Y10T29/49121 ,  Y10T29/49169 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A resin sealed electronic device has an electronic element (30), a first external lead (10) with an element placement pad (11) having a thickness t of less than 0.1 mm, and a second external lead (20), which is disposed at a distance from the element placement pad (11), the first external lead (10) being bent into an S shape, the bending depth d thereof being made at least the thickness t of the first external lead (10), and the thickness T of the sealing resin on the non-element side of the element placement pad (11) being made smaller than the bending depth d. The electronic element (30), part of the first external lead (10), and part of the second external lead (20) are sealed by a sealing resin(40). This structure provides a compact electronic device, the vertical, horizontal, and height dimensions of which are all under 1 mm.

Abstract translation: 树脂密封电子器件具有电子元件（30），具有厚度t小于0.1mm的元件放置垫（11）的第一外部引线（10）和设置在第二外部引线（20）上的第二外部引线 在距离元件放置垫（11）一定距离处，第一外部引线（10）弯曲成S形，其弯曲深度d至少为第一外部引线（10）的厚度t，厚度 元件放置垫（11）的非元件侧上的密封树脂的T小于弯曲深度d。 电子元件（30），第一外部引线（10）的一部分和第二外部引线（20）的一部分由密封树脂（40）密封。 这种结构提供了紧凑的电子设备，其垂直，水平和高度的尺寸都在1毫米以下。

公开(公告)号：US20010008360A1

公开(公告)日：2001-07-19

申请号：US09761505

申请日：2001-01-16

Applicant: MATSUSHITA ELECTRONICS CORPORATION

Inventor： Hiromichi Tsuji

IPC: H01J029/80

CPC classification number: H01J29/07 ,  H01J2229/075

Abstract: A cathode ray tube capable of reducing the shifting of apertures in the horizontal direction of the screen during the operation of the cathode ray tube, thereby preventing a color displacement, unevenness in colors, and reduction in luminance from occurring. By taking a center line of a shadow mask in a horizontal direction as an X-axis and a center line of the shadow mask in a vertical direction as a Y-axis, bridges in the vicinity of both ends of a perforated portion in the X-axis direction have a greater arrangement pitch in the vertical direction than that of bridges in the vicinity of a Y-axis. Accordingly, when a tension force is applied in the Y-axis direction to the shadow mask so that the shadow mask is stretched and held, a displacement of the aperture lines in the X-axis direction in the vicinity of both the ends of the shadow mask in the X-axis direction is suppressed to a small value, thereby reducing the shifting of the apertures in the X-axis direction during the operation of the cathode ray tube. This serves to prevent a color displacement, unevenness in colors, and reduction in luminance from occurring, and in addition, the occurrence of wrinkles in the shadow mask at the time when the shadow mask is stretched and held can be prevented.

Abstract translation: 一种阴极射线管，其能够在阴极射线管的操作期间减少屏幕的水平方向上的孔的偏移，从而防止颜色偏移，颜色不均匀以及亮度的降低。 通过将荫罩的水平方向的中心线作为Y轴的垂直方向的X轴和荫罩的中心线，在X的穿孔部的两端附近， 轴方向在垂直方向上具有比在Y轴附近的桥的间距更大的排列间距。 因此，当沿着Y轴方向向荫罩施加张力使得荫罩被拉伸和保持时，在阴影两端附近的X轴方向上的孔径线的位移 掩模在X轴方向被抑制到较小的值，从而在阴极射线管的操作期间减小了X轴方向上的孔的偏移。 这用于防止颜色偏移，颜色不均匀和亮度降低，并且此外，可以防止在荫罩被拉伸和保持时在荫罩中出现褶皱。