公开(公告)号：US08086919B2

公开(公告)日：2011-12-27

申请号：US12470799

申请日：2009-05-22

Applicant: Ban-Hui Chen ,  Wei-Chen Teo ,  Min-Cheng Wang

Inventor： Ban-Hui Chen ,  Wei-Chen Teo ,  Min-Cheng Wang

IPC: G11C29/00

CPC classification number: G11C29/16 ,  G11C16/04 ,  G11C2029/0401

Abstract: A flash memory controller having a flash memory testing functions is provided, in which the flash memory controller includes a microprocessor unit, a flash memory interface unit, a host interface unit and a memory cell testing unit. The flash memory interface unit is configured for connecting a plurality of flash memory chips, where each flash memory chip has a plurality of flash memory dies and each flash memory die has a plurality of physical blocks. The host interface unit is configured for connecting a host system. The memory cell testing unit is configured for determining whether the physical blocks can be normally written, read and erased. Accordingly, the flash memory controller can perform a flash memory testing under a command of the host system and all the physical blocks of the flash memory chip can be tested during the flash memory testing.

Abstract translation: 提供了一种具有闪存测试功能的闪存控制器，其中闪存控制器包括微处理器单元，闪存接口单元，主机接口单元和存储单元测试单元。 闪速存储器接口单元被配置用于连接多个闪速存储器芯片，其中每个闪速存储器芯片具有多个闪速存储器管芯，并且每个闪速存储器管芯具有多个物理块。 主机接口单元被配置为连接主机系统。 存储单元测试单元被配置用于确定物理块是否能够正常写入，读取和擦除。 因此，闪存控制器可以在主机系统的命令下执行闪存测试，并且可以在闪存测试期间测试闪存芯片的所有物理块。

公开(公告)号：US20110252630A1

公开(公告)日：2011-10-20

申请号：US13032656

申请日：2011-02-23

Applicant: GANG-TAO GU ,  ZHONG-HAI XIAO ,  MIN-CHENG WANG

Inventor： GANG-TAO GU ,  ZHONG-HAI XIAO ,  MIN-CHENG WANG

IPC: G01R31/28 ,  B23P21/00

CPC classification number: G02F1/133603 ,  Y10T29/49004 ,  Y10T29/5136 ,  Y10T29/5137 ,  Y10T29/53022 ,  Y10T29/5313 ,  Y10T29/53174 ,  Y10T29/53183 ,  Y10T29/53187

Abstract: A manufacturing apparatus for a backlight unit includes a feed mechanism, a testing mechanism, and an attachment mechanism. The feed mechanism arranges a plurality of light-emitting diodes in a row. The testing mechanism tests the light-emitting diodes. The attachment mechanism positions the light-emitting diodes to a circuit board. The attachment mechanism comprises a support assembly and a laminating device, in which the support assembly receives the light-emitting diodes tested by the at least one testing unit, the support assembly is opposite to the circuit board, and the laminating device laminates the light-emitting diodes to the circuit board. A method for manufacturing the backlight unit is also provided.

Abstract translation: 用于背光单元的制造装置包括进给机构，测试机构和附接机构。 进给机构将多个发光二极管排成一列。 测试机构测试发光二极管。 附接机构将发光二极管定位到电路板。 所述附接机构包括支撑组件和层压装置，其中所述支撑组件接收由所述至少一个测试单元测试的所述发光二极管，所述支撑组件与所述电路板相对，并且所述层压装置将所述发光二极管层叠， 发光二极管到电路板。 还提供了制造背光单元的方法。

公开(公告)号：US20100241914A1

公开(公告)日：2010-09-23

申请号：US12470799

申请日：2009-05-22

Applicant: BAN-HUI CHEN ,  Wei-Chen Teo ,  Min-Cheng Wang

Inventor： BAN-HUI CHEN ,  Wei-Chen Teo ,  Min-Cheng Wang

IPC: G11C29/04 ,  G06F12/02 ,  G06F12/00 ,  G06F11/16

CPC classification number: G11C29/16 ,  G11C16/04 ,  G11C2029/0401

Abstract: A flash memory controller having a flash memory testing functions is provided, in which the flash memory controller includes a microprocessor unit, a flash memory interface unit, a host interface unit and a memory cell testing unit. The flash memory interface unit is configured for connecting a plurality of flash memory chips, where each flash memory chip has a plurality of flash memory dies and each flash memory die has a plurality of physical blocks. The host interface unit is configured for connecting a host system. The memory cell testing unit is configured for determining whether the physical blocks can be normally written, read and erased. Accordingly, the flash memory controller can perform a flash memory testing under a command of the host system and all the physical blocks of the flash memory chip can be tested during the flash memory testing.

Abstract translation: 提供了一种具有闪存测试功能的闪存控制器，其中闪存控制器包括微处理器单元，闪存接口单元，主机接口单元和存储单元测试单元。 闪速存储器接口单元被配置用于连接多个闪速存储器芯片，其中每个闪速存储器芯片具有多个闪速存储器管芯，并且每个闪速存储器管芯具有多个物理块。 主机接口单元被配置为连接主机系统。 存储单元测试单元被配置用于确定物理块是否能够正常写入，读取和擦除。 因此，闪存控制器可以在主机系统的命令下执行闪存测试，并且可以在闪存测试期间测试闪存芯片的所有物理块。

公开(公告)号：US20100151554A1

公开(公告)日：2010-06-17

申请号：US12636734

申请日：2009-12-12

Applicant: Min-Cheng Wang ,  Raphael Chiou

Inventor： Min-Cheng Wang ,  Raphael Chiou

IPC: C02F3/34 ,  C12N9/02 ,  C12N9/10

CPC classification number: C12N9/0008 ,  C12N9/0051 ,  C12N9/0061 ,  C12N9/1025

Abstract: The present invention provides an enzyme composition and a method for treating coal using the enzyme composition. The enzyme composition includes at least one enzyme, coenzyme and ammonium acetate, wherein the enzyme can be laccase-isozyme, pyruvate dehydrogenase, dihydrolipoyl transacetylase, and dihydrolipoyl dehydrogenase, and the coenzyme can be CoA, CoA-SH, thiamine pyrophosphate, lipoic acid, flavin adenine dinucleotide, and nicotinamide adenine dinucleotide. In addition, the method of the present invention includes treating the coal with the enzyme composition for more than 72 hours.

Abstract translation: 本发明提供一种酶组合物和使用该酶组合物处理煤的方法。 所述酶组合物包括至少一种酶，辅酶和乙酸铵，其中所述酶可以是漆酶同功酶，丙酮酸脱氢酶，二氢硫辛酰基转乙酰酶和二氢胆脂酰脱氢酶，并且所述辅酶可以是CoA，CoA-SH，焦硫磷酸硫胺素，硫辛酸， 黄素腺嘌呤二核苷酸和烟酰胺腺嘌呤二核苷酸。 此外，本发明的方法包括用酶组合物处理煤超过72小时。

公开(公告)号：US07515238B2

公开(公告)日：2009-04-07

申请号：US11516341

申请日：2006-09-06

Applicant: Kuan-Hsin Chen ,  Keng-Ming Lai ,  Chih-Hung Hsiao ,  Min-Cheng Wang

Inventor： Kuan-Hsin Chen ,  Keng-Ming Lai ,  Chih-Hung Hsiao ,  Min-Cheng Wang

IPC: G02F1/1345

CPC classification number: H05K3/323 ,  G02F1/13452 ,  H05K1/142 ,  H05K3/361 ,  H05K2201/10674

Abstract: An exemplary liquid crystal panel (100) includes a first substrate (110), a second substrate (120) opposite to the first substrate, a liquid crystal layer (130) sandwiched between the first and second substrates, a plurality of drive integrated circuits (ICs) (114), and a plurality of anisotropic conductive film (ACF) units (115). The first substrate includes a source bonding region (117) and a gate bonding region (118) at the periphery thereof. Each of the source bonding region and the gate bonding region includes a plurality of connecting regions and a plurality of spacing regions each between two connecting regions. The ACF units are disposed on the connecting regions of the source bonding region and the gate bonding region, and are configured for bonding the drive ICs onto the first substrate.

Abstract translation: 示例性液晶面板（100）包括第一基板（110），与第一基板相对的第二基板（120），夹在第一和第二基板之间的液晶层（130），多个驱动集成电路 IC）（114）和多个各向异性导电膜（ACF）单元（115）。 第一基板在其周边包括源极接合区域（117）和栅极接合区域（118）。 源极接合区域和栅极接合区域中的每一个包括在两个连接区域之间的多个连接区域和多个间隔区域。 ACF单元设置在源极接合区域和栅极接合区域的连接区域上，并被配置为将驱动IC接合到第一基板上。

公开(公告)号：US20120105776A1

公开(公告)日：2012-05-03

申请号：US13073013

申请日：2011-03-28

Applicant: CHIH-WEI LIN ,  Min-Cheng Wang ,  Chih-Yu Hsu

Inventor： CHIH-WEI LIN ,  Min-Cheng Wang ,  Chih-Yu Hsu

IPC: G02F1/1335 ,  H01J9/26

CPC classification number: G02F1/1339 ,  G02F2001/13415

Abstract: A liquid crystal display panel includes a transistor array substrate, a color filter substrate, a liquid crystal layer, and a sealant material. The transistor array substrate includes a transparent substrate, a transistor array, and a plurality of peripheral wires. The transparent substrate has a display region and a non-display region, and the non-display region is located beside the display region. The transistor array is disposed in the display region. The peripheral wires are disposed in the non-display region and electrically connected with the transistor array. A transmittance of the non-display region is less than 30%. The liquid crystal layer is disposed between the color filter substrate and the transistor array substrate. The sealant material is disposed in the non-display region and connected between the color filter substrate and the transistor array substrate. The sealant material surrounds the liquid crystal layer.

Abstract translation: 液晶显示面板包括晶体管阵列基板，滤色器基板，液晶层和密封材料。 晶体管阵列基板包括透明基板，晶体管阵列和多个外围导线。 透明基板具有显示区域和非显示区域，非显示区域位于显示区域的旁边。 晶体管阵列设置在显示区域中。 外围导线配置在非显示区域并与晶体管阵列电连接。 非显示区域的透射率小于30％。 液晶层设置在滤色器基板和晶体管阵列基板之间。 密封剂材料设置在非显示区域中并且连接在滤色器基板和晶体管阵列基板之间。 密封材料围绕着液晶层。

公开(公告)号：US20070052905A1

公开(公告)日：2007-03-08

申请号：US11516341

申请日：2006-09-06

Applicant: Kuan-Hsin Chen ,  Keng-Ming Lai ,  Chih-Hung Hsiao ,  Min-Cheng Wang

Inventor： Kuan-Hsin Chen ,  Keng-Ming Lai ,  Chih-Hung Hsiao ,  Min-Cheng Wang

IPC: G02F1/1345

CPC classification number: H05K3/323 ,  G02F1/13452 ,  H05K1/142 ,  H05K3/361 ,  H05K2201/10674

Abstract: An exemplary liquid crystal panel (100) includes a first substrate (110), a second substrate (120) opposite to the first substrate, a liquid crystal layer (130) sandwiched between the first and second substrates, a plurality of drive integrated circuits (ICs) (114), and a plurality of anisotropic conductive film (ACF) units (115). The first substrate includes a source bonding region (117) and a gate bonding region (118) at the periphery thereof. Each of the source bonding region and the gate bonding region includes a plurality of connecting regions and a plurality of spacing regions each between two connecting regions. The ACF units are disposed on the connecting regions of the source bonding region and the gate bonding region, and are configured for bonding the drive ICs onto the first substrate.

Abstract translation: 示例性液晶面板（100）包括第一基板（110），与第一基板相对的第二基板（120），夹在第一和第二基板之间的液晶层（130），多个驱动集成电路 IC）（114）和多个各向异性导电膜（ACF）单元（115）。 第一基板在其周边包括源极接合区域（117）和栅极接合区域（118）。 源极接合区域和栅极接合区域中的每一个包括在两个连接区域之间的多个连接区域和多个间隔区域。 ACF单元设置在源极接合区域和栅极接合区域的连接区域上，并被配置为将驱动IC接合到第一基板上。

公开(公告)号：US08605235B2

公开(公告)日：2013-12-10

申请号：US12779915

申请日：2010-05-13

Applicant: Chih-Wei Lin ,  Min-Cheng Wang ,  Yung-Cheng Chen ,  Hung-Min Liu

Inventor： Chih-Wei Lin ,  Min-Cheng Wang ,  Yung-Cheng Chen ,  Hung-Min Liu

IPC: G02F1/1335

CPC classification number: G01B11/24 ,  G01B5/061 ,  G01B11/00 ,  G01B11/02 ,  G01B11/0608 ,  G01B11/08 ,  G01B17/02 ,  G02F1/133512 ,  G02F1/13394 ,  G03F7/70625

Abstract: A display device and a method of measuring a surface structure of the same are provided. The display device includes first and second substrates, first and second patterned light-shielding layers, and first and second pixel units. The first patterned light-shielding layer disposed on a surface of the first substrate includes first openings. The second patterned light-shielding layer disposed on the surface of the first substrate in the first patterned light-shielding layer includes second openings. The first pixel unit includes first and second protrusions. The first protrusion correspondingly covers the first openings and a portion of the first patterned light-shielding layer. The second protrusion is disposed in the first and second patterned light-shielding layers. The second pixel unit includes a third protrusion correspondingly covering the second openings and a portion of the second patterned light-shielding layer, wherein sizes of the second openings are smaller than sizes of the first openings.

Abstract translation: 提供显示装置和测量其表面结构的方法。 显示装置包括第一和第二基板，第一和第二图案化遮光层以及第一和第二像素单元。 设置在第一基板的表面上的第一图案化遮光层包括第一开口。 设置在第一图案化遮光层中的第一基板的表面上的第二图案遮光层包括第二开口。 第一像素单元包括第一和第二突起。 第一突起相应地覆盖第一开口和第一图案化遮光层的一部分。 第二突起设置在第一和第二图案化的遮光层中。 第二像素单元包括对应地覆盖第二开口的第三突起和第二图案化遮光层的一部分，其中第二开口的尺寸小于第一开口的尺寸。

公开(公告)号：US20120105789A1

公开(公告)日：2012-05-03

申请号：US13008474

申请日：2011-01-18

Applicant: Chih-Wei LIN ,  Min-Cheng Wang ,  Yu-Lun Hsueh

Inventor： Chih-Wei LIN ,  Min-Cheng Wang ,  Yu-Lun Hsueh

IPC: G02F1/1339

CPC classification number: G02F1/13392 ,  G02F2001/13396

Abstract: A display substrate includes a plate and a plurality of spacers. The plate has a plate surface, and the plate surface is divided into a central region and a peripheral region, wherein the peripheral region surrounds the central region. The spacers are disposed on the plate surface in an aperiodic arrangement manner. A number of the spacers located in the central region is M, and a number of the spacers located in the peripheral region is N. An area of the central region is X, and an area of the peripheral region is Y. X, Y, M, and N satisfy the following mathematical expression: M X ≥ N Y .

Abstract translation: 显示基板包括板和多个间隔件。 板具有板表面，并且板表面被分成中心区域和周边区域，其中周边区域围绕中心区域。 间隔件以非周期的排列方式设置在板表面上。 位于中央区域的多个间隔物为M，并且位于周边区域中的多个间隔物为N.中心区域的面积为X，外围区域的面积为Y.X，Y， M和N满足以下数学表达式：MX≥NY。

公开(公告)号：US08505189B2

公开(公告)日：2013-08-13

申请号：US13032656

申请日：2011-02-23

Applicant: Gang-Tao Gu ,  Zhong-Hai Xiao ,  Min-Cheng Wang

Inventor： Gang-Tao Gu ,  Zhong-Hai Xiao ,  Min-Cheng Wang

IPC: B23P23/00

CPC classification number: G02F1/133603 ,  Y10T29/49004 ,  Y10T29/5136 ,  Y10T29/5137 ,  Y10T29/53022 ,  Y10T29/5313 ,  Y10T29/53174 ,  Y10T29/53183 ,  Y10T29/53187

Abstract: A manufacturing apparatus for a backlight unit includes a feed mechanism, a testing mechanism, and an attachment mechanism. The feed mechanism arranges a plurality of light-emitting diodes in a row. The testing mechanism tests the light-emitting diodes. The attachment mechanism positions the light-emitting diodes to a circuit board. The attachment mechanism comprises a support assembly and a laminating device, in which the support assembly receives the light-emitting diodes tested by the at least one testing unit, the support assembly is opposite to the circuit board, and the laminating device laminates the light-emitting diodes to the circuit board. A method for manufacturing the backlight unit is also provided.

Abstract translation: 用于背光单元的制造装置包括进给机构，测试机构和附接机构。 进给机构将多个发光二极管排成一列。 测试机构测试发光二极管。 附接机构将发光二极管定位到电路板。 所述附接机构包括支撑组件和层压装置，其中所述支撑组件接收由所述至少一个测试单元测试的所述发光二极管，所述支撑组件与所述电路板相对，并且所述层压装置将所述发光二极管层叠， 发光二极管到电路板。 还提供了制造背光单元的方法。