公开(公告)号：US08441809B2

公开(公告)日：2013-05-14

申请号：US13161538

申请日：2011-06-16

Applicant: Ravi Mahajan ,  Sandeep Sane

Inventor： Ravi Mahajan ,  Sandeep Sane

IPC: H05K7/02 ,  H01L21/78 ,  H01L21/50

CPC classification number: H05K1/142 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15192 ,  H05K1/141 ,  H05K1/181 ,  H05K1/183 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05647

Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

Abstract translation: 微电子封装包括衬底（110），嵌入衬底中的硅贴片（120），在硅贴片的第一位置处的第一互连结构（131）和在第二位置处的第二互连结构（132） 硅贴片以及将第一互连结构和第二互连结构彼此连接的硅贴片中的导电线（150）。

公开(公告)号：US08064224B2

公开(公告)日：2011-11-22

申请号：US12059133

申请日：2008-03-31

Applicant: Ravi Mahajan ,  Sandeep Sane

Inventor： Ravi Mahajan ,  Sandeep Sane

IPC: H05K7/02 ,  H01L21/78 ,  H01L21/50

CPC classification number: H05K1/142 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15192 ,  H05K1/141 ,  H05K1/181 ,  H05K1/183 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05647

Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

Abstract translation: 微电子封装包括衬底（110），嵌入衬底中的硅贴片（120），在硅贴片的第一位置处的第一互连结构（131）和在第二位置处的第二互连结构（132） 硅贴片以及将第一互连结构和第二互连结构彼此连接的硅贴片中的导电线（150）。

公开(公告)号：US20090065932A1

公开(公告)日：2009-03-12

申请号：US11853752

申请日：2007-09-11

Applicant: Sandeep Sane ,  Nachiket Raravikar

Inventor： Sandeep Sane ,  Nachiket Raravikar

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H01L21/563 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3157 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1182 ,  H01L2224/11827 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13687 ,  H01L2224/13693 ,  H01L2224/16225 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2224/831 ,  H01L2224/83379 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include coating an interconnect structure disposed on a die with a layer of functionalized nanoparticles, wherein the functionalized nanoparticles are dispersed in a solvent, heating the layer of functionalized nanoparticles to drive off a portion of the solvent, and applying an underfill on the coated interconnect structure.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括用功能化纳米颗粒层涂布设置在管芯上的互连结构，其中官能化纳米颗粒分散在溶剂中，加热功能化纳米颗粒层以驱除溶剂的一部分，并将底部填充物 涂层互连结构。

公开(公告)号：US20070138621A1

公开(公告)日：2007-06-21

申请号：US11305527

申请日：2005-12-16

Applicant: Sandeep Sane ,  Nitin Deshpande ,  Chia-Pin Chiu

Inventor： Sandeep Sane ,  Nitin Deshpande ,  Chia-Pin Chiu

IPC: H01L23/12

CPC classification number: H01L23/4275 ,  H01L24/32 ,  H01L2224/73253 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/14 ,  H01L2924/1433

Abstract: A method, apparatus and system with a semiconductor package including a thermal interface material dam enclosing a volume of thermal interface material.

公开(公告)号：US20080079129A1

公开(公告)日：2008-04-03

申请号：US11540045

申请日：2006-09-29

Applicant: Shankar Ganapathysubramanian ,  Sandeep Sane

Inventor： Shankar Ganapathysubramanian ,  Sandeep Sane

IPC: H01L21/00

CPC classification number: H01L23/34 ,  H01L23/40 ,  H01L2023/4081 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor packages and methods to fabricate thereof are described. A decoupling assembly is disposed between a package substrate and a circuit board. The decoupling assembly engages in response to a stimulus such that a semiconductor die is de-coupled from a socket and a circuit board. The decoupling assembly engages in response to a stimulus such that a semiconductor die is decoupled from a substrate. A decoupling assembly includes a clamping device, springs, and shape memory alloy rods. The shape memory alloy rods are actuators that generate motion or a pre-programmed shape to apply force when thermally excited. When the thermal excitation or other stimulus is removed, the shape memory alloy rods tend to return to their original shape, thus relieving any load or motion generated.

Abstract translation: 对半导体封装及其制造方法进行说明。 解耦组件设置在封装衬底和电路板之间。 解耦组件响应于刺激而接合，使得半导体管芯从插座和电路板脱耦合。 解耦组件响应于刺激而接合，使得半导体管芯与衬底去耦合。 解耦组件包括夹紧装置，弹簧和形状记忆合金棒。 形状记忆合金棒是产生运动或预编程形状的致动器，以在热激发时施加力。 当热激发或其他刺激被去除时，形状记忆合金棒倾向于返回到其原始形状，从而减轻产生的任何负载或运动。

公开(公告)号：US20060214313A1

公开(公告)日：2006-09-28

申请号：US11089050

申请日：2005-03-24

Applicant: Ruel Pieda ,  Carmelito Libay ,  Andrew Gomez ,  Sandeep Sane ,  Timothy Takeuchi

Inventor： Ruel Pieda ,  Carmelito Libay ,  Andrew Gomez ,  Sandeep Sane ,  Timothy Takeuchi

IPC: H01L23/28

CPC classification number: H01L24/83 ,  H01L23/3121 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method for packaging a die includes attaching the die to a substrate using a plurality of pieces of discontinuous die attach material, and injecting a mold compound at the interface between the die and the substrate.

Abstract translation: 包装模具的方法包括使用多个不连续的芯片附着材料将模具附着到基板上，以及在模具和基板之间的界面处注入模具化合物。

公开(公告)号：US20060199299A1

公开(公告)日：2006-09-07

申请号：US11072112

申请日：2005-03-03

Applicant: Nitin Deshpande ,  Sandeep Sane

Inventor： Nitin Deshpande ,  Sandeep Sane

IPC: H01L21/00

CPC classification number: H01L21/4882 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method and apparatus for mounting semiconductor die and integral heat spreader are disclosed. In one embodiment, thermal expansion of the integral heat spreader is restricted by physical constraints during the process of heating interface material that bonds the integral heat spreader and semiconductor die together. In an alternative embodiment, thermal expansion of the integral hat spreader is restricted by applying an external compressive force to the integral heat spreader while heating interface material that bonds the integral heat spreader and semiconductor die together.

Abstract translation: 公开了一种用于安装半导体管芯和整体散热器的方法和装置。 在一个实施例中，整体散热器的热膨胀在加热将整体式散热器和半导体管芯结合在一起的界面材料的加工过程中受到物理限制。 在替代实施例中，通过对整体散热器施加外部压缩力同时加热将整体散热器和半导体管芯结合在一起的界面材料加热来限制整体帽扩展器的热膨胀。

公开(公告)号：US20060220195A1

公开(公告)日：2006-10-05

申请号：US11095693

申请日：2005-03-31

Applicant: Sandeep Sane

Inventor： Sandeep Sane

IPC: H01L21/00 ,  H01L23/495

CPC classification number: H01L21/563 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A silicon die having a junction side being attachable to a substrate, a backside surface spaced from the junction side and an underfill control feature to prevent an underfill from settling above said backside surface is disclosed herein.

Abstract translation: 本文公开了具有可连接到基板的接合侧的硅管芯，与接合侧间隔开的后侧表面和用于防止底部填充物沉积在所述背面上方的底部填充控制特征。

公开(公告)号：US20090244874A1

公开(公告)日：2009-10-01

申请号：US12059133

申请日：2008-03-31

Applicant: Ravi Mahajan ,  Sandeep Sane

Inventor： Ravi Mahajan ,  Sandeep Sane

IPC: H05K7/02 ,  H01L21/50

CPC classification number: H05K1/142 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15192 ,  H05K1/141 ,  H05K1/181 ,  H05K1/183 ,  H05K2201/0187 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05647

Abstract: A microelectronic package comprises a substrate (110), a silicon patch (120) embedded in the substrate, a first interconnect structure (131) at a first location of the silicon patch and a second interconnect structure (132) at a second location of the silicon patch, and an electrically conductive line (150) in the silicon patch connecting the first interconnect structure and the second interconnect structure to each other.

Abstract translation: 微电子封装包括衬底（110），嵌入衬底中的硅贴片（120），在硅贴片的第一位置处的第一互连结构（131）和在第二位置处的第二互连结构（132） 硅贴片以及将第一互连结构和第二互连结构彼此连接的硅贴片中的导电线（150）。

公开(公告)号：US20080057628A1

公开(公告)日：2008-03-06

申请号：US11930760

申请日：2007-10-31

Applicant: Sandeep Sane ,  Biju Chandran

Inventor： Sandeep Sane ,  Biju Chandran

IPC: H01L21/58

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L21/563 ,  H01L24/28 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/00

Abstract: A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.

Abstract translation: 一种用于组装用于半导体器件的封装的方法，其包括通过将所述管芯和所述衬底加热至所述焊料回流的温度，降低到所选择的环氧树脂将固化的温度，从而使包封期间的内部电介质层中的应力降低 将液化环氧树脂加入到模具和基材中，并将模具和基材保持在环氧树脂固化一定时间的温度。