公开(公告)号：US08236691B2

公开(公告)日：2012-08-07

申请号：US12347721

申请日：2008-12-31

Applicant: Yakov Shor ,  Semeon Altshuler ,  Maor Rotlain ,  Yigal Alon ,  Dror Horvitz

Inventor： Yakov Shor ,  Semeon Altshuler ,  Maor Rotlain ,  Yigal Alon ,  Dror Horvitz

IPC: H01L21/60

CPC classification number: H01L21/28568 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76879

Abstract: A method of plug fill for high aspect ratio plugs wherein a nucleation layer is formed at a bottom of a via and not on the sidewalls. The plug fill is in the direction from bottom to top of the via and not inwards from the sidewalls. The resulting plug is voidless and seamless.

Abstract translation: 一种用于高纵横比插塞的塞子填充方法，其中成核层形成在通孔的底部而不是在侧壁上。 塞子填充沿着通孔的底部到顶部的方向，而不是从侧壁向内。 所产生的插头是无效的和无缝的。

公开(公告)号：US20090302477A1

公开(公告)日：2009-12-10

申请号：US12156999

申请日：2008-06-06

Applicant: Yakov Shor ,  Yuval Najari ,  Lior Gadot ,  Effi Aboody ,  Semeon Altshuler ,  Nuriel Amir

Inventor： Yakov Shor ,  Yuval Najari ,  Lior Gadot ,  Effi Aboody ,  Semeon Altshuler ,  Nuriel Amir

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/485 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In some embodiments, disclosed is an interconnect structure with embedded plugs.

Abstract translation: 在一些实施例中，公开了具有嵌入式插头的互连结构。

公开(公告)号：US07510907B2

公开(公告)日：2009-03-31

申请号：US11165465

申请日：2005-06-22

Applicant: John Heck ,  Qing Ma ,  Quan Tran ,  Tsung-Kuan Allen Chou ,  Semeon Altshuler ,  Boaz Weinfeld

Inventor： John Heck ,  Qing Ma ,  Quan Tran ,  Tsung-Kuan Allen Chou ,  Semeon Altshuler ,  Boaz Weinfeld

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and method of fabricating a through-wafer via. A first mask is formed over a first side of a first semiconductor die to define a first via area. A deep recess is etched through the first semiconductor die in the first via area and a blanket metal layer is formed over the first side including the deep recess. The blanket metal layer is removed from an outer surface of the first side of the first semiconductor die while retaining a portion of the blanket metal layer within the deep recess.

Abstract translation: 一种制造通晶片通孔的装置和方法。 第一掩模形成在第一半导体管芯的第一侧上以限定第一通孔区域。 通过第一通孔区域中的第一半导体管芯蚀刻深的凹部，并且在包括深凹部的第一侧上形成覆盖金属层。 将橡皮布金属层从第一半导体管芯的第一侧的外表面移除，同时将橡皮布金属层的一部分保持在深凹部内。

公开(公告)号：US20060289967A1

公开(公告)日：2006-12-28

申请号：US11165465

申请日：2005-06-22

Applicant: John Heck ,  Qing Ma ,  Quan Tran ,  Tsung-Kuan Chou ,  Semeon Altshuler ,  Boaz Weinfeld

Inventor： John Heck ,  Qing Ma ,  Quan Tran ,  Tsung-Kuan Chou ,  Semeon Altshuler ,  Boaz Weinfeld

IPC: H01L29/40 ,  H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and method of fabricating a through-wafer via. A first mask is formed over a first side of a first semiconductor die to define a first via area. A deep recess is etched through the first semiconductor die in the first via area and a blanket metal layer is formed over the first side including the deep recess. The blanket metal layer is removed from an outer surface of the first side of the first semiconductor die while retaining a portion of the blanket metal layer within the deep recess.

公开(公告)号：US07935627B1

公开(公告)日：2011-05-03

申请号：US12398298

申请日：2009-03-05

Applicant: Yakov Shor ,  Semeon Altshuler ,  Valery Shumilin ,  Alexander Ripp

Inventor： Yakov Shor ,  Semeon Altshuler ,  Valery Shumilin ,  Alexander Ripp

IPC: H01L21/4763 ,  H01L23/48

CPC classification number: H01L21/76814 ,  H01L21/02321 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76826 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In some embodiments, a damascene structure may be formed with metal lines separated by a dielectric layer. Portions of the dielectric layer may be ion implanted with carbon and/or inert species to lower selectively the dielectric constant, while leaving the bulk of the dielectric layer unaffected by the implant. As a result, suitably low dielectric constants can be achieved in damascene dielectric layers with sufficient mechanical strength.

Abstract translation: 在一些实施例中，可以用金属线形成镶嵌结构，金属线由电介质层分开。 介电层的一部分可以用碳和/或惰性物质离子注入，以选择性地降低介电常数，同时使绝缘层的体积不受植入物的影响。 结果，在具有足够的机械强度的镶嵌介电层中可以实现适当的低介电常数。

公开(公告)号：US20100167532A1

公开(公告)日：2010-07-01

申请号：US12347721

申请日：2008-12-31

Applicant: Yakov Shor ,  Semeon Altshuler ,  Maor Rotlain ,  Yigal Alon ,  Dror Horvitz

Inventor： Yakov Shor ,  Semeon Altshuler ,  Maor Rotlain ,  Yigal Alon ,  Dror Horvitz

IPC: H01L21/60

CPC classification number: H01L21/28568 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76879

Abstract: A method of plug fill for high aspect ratio plugs wherein a nucleation layer is formed at a bottom of a via and not on the sidewalls. The plug fill is in the direction from bottom to top of the via and not inwards from the sidewalls. The resulting plug is voidless and seamless.

Abstract translation: 一种用于高纵横比插塞的塞子填充方法，其中成核层形成在通孔的底部而不是在侧壁上。 塞子填充沿着通孔的底部到顶部的方向，而不是从侧壁向内。 所产生的插头是无效的和无缝的。