公开(公告)号：US06964885B2

公开(公告)日：2005-11-15

申请号：US10752255

申请日：2004-01-06

Applicant: Patrick Anthony Coico ,  James H. Covell ,  Benjamin V. Fasano ,  Lewis S. Goldman ,  Ronald L. Hering ,  Sundar Kamath ,  Kenneth Charles Marston ,  Frank Louis Pompeo ,  Karl J. Puttlitz ,  Jeffrey Allen Zitz

Inventor： Patrick Anthony Coico ,  James H. Covell ,  Benjamin V. Fasano ,  Lewis S. Goldman ,  Ronald L. Hering ,  Sundar Kamath ,  Kenneth Charles Marston ,  Frank Louis Pompeo ,  Karl J. Puttlitz ,  Jeffrey Allen Zitz

IPC: H01L21/50 ,  H01L23/04 ,  H01L25/065 ,  H05K1/02 ,  H05K3/30 ,  H01L21/44 ,  H01L21/48

CPC classification number: H01L21/50 ,  H01L23/04 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/301 ,  H01L2224/0401

Abstract: An integrated circuit module, a land grid array module, and a method for forming the module, include a substrate, which mounts one or more chips or discrete electronic components, and a cap for covering the substrate, and including at least one protrusion coupled to the cap for limiting the amount of flexing of the substrate during actuation. The at least one protrusion can be either rigidly fixed to the cap or adjustably inserted through the cap.

Abstract translation: 集成电路模块，焊盘栅阵列模块以及用于形成模块的方法包括安装一个或多个芯片或分立电子部件的基板以及用于覆盖基板的盖，并且包括至少一个连接到 用于在致动期间限制基板的弯曲量的盖。 所述至少一个突起可以刚性地固定到盖上或者可调节地插入通过盖。

公开(公告)号：US06317331B1

公开(公告)日：2001-11-13

申请号：US09375175

申请日：1999-08-16

Applicant: Sundar Kamath ,  David Chazan ,  Solomon I. Beilin

Inventor： Sundar Kamath ,  David Chazan ,  Solomon I. Beilin

IPC: H05K118

CPC classification number: H01L23/5383 ,  H01L23/3735 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/351 ,  H05K1/0271 ,  H05K1/0272 ,  H05K2201/0133 ,  H05K2201/068 ,  H05K2201/09109 ,  H05K2201/10416 ,  H05K2201/10734 ,  Y10T428/24926 ,  H01L2224/0401

Abstract: A wiring substrate with reduced thermal expansion. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or a BGA package. The wiring substrate has a thermal expansion reduction insert in a thermal expansion stress region where the integrated circuit is mounted. The thermal expansion reduction insert may extend a selected distance from the edge or edges of the integrated circuit attachment area, or stop a selected distance from the edge or edges of the integrated circuit attachment area, or be essentially equal to the integrated circuit attachment area. The thermal expansion reduction insert reduces the thermal expansion of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In a specific embodiment, the wiring substrate is a laminated printed wiring board with the thermal expansion reduction insert in a layer next to an outer layer to which the integrated circuit is joined (mounted). In a further embodiment the thermal stress reduction insert is a CIC insert or a copper-molybdenum insert. In an alternative embodiment, the wiring substrate is a thin film substrate or a VLSI substrate.

Abstract translation: 具有降低的热膨胀的布线基板。 诸如层叠PWB，薄膜电路，引线框架或芯片载体的布线基板可以接受诸如管芯，倒装芯片或BGA封装的集成电路。 布线基板在安装有集成电路的热膨胀应力区域中具有热膨胀降低插入件。 热膨胀减小插入件可以从集成电路附接区域的边缘或边缘延伸选定的距离，或者停止从集成电路连接区域的边缘或边缘选择的距离，或者基本上等于集成电路连接区域。 热膨胀减少插入物减少了与集成电路接合的区域中的布线基板的热膨胀，从而降低了布线基板集成电路组件的部件之间的热应力。 在具体实施方式中，布线基板是层叠印刷线路板，其中热膨胀降低插入件位于与集成电路接合（安装）的外层相邻的层中。 在另一实施例中，热应力减小插入件是CIC插入件或铜 - 钼插入件。 在替代实施例中，布线基板是薄膜基板或VLSI基板。

公开(公告)号：US06509529B2

公开(公告)日：2003-01-21

申请号：US09960164

申请日：2001-09-20

Applicant: Sundar Kamath ,  David Chazan ,  Jan I. Strandberg ,  Solomon I. Beilin

Inventor： Sundar Kamath ,  David Chazan ,  Jan I. Strandberg ,  Solomon I. Beilin

IPC: H05K103

CPC classification number: H05K1/0271 ,  H01L23/3735 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/0272 ,  H05K2201/0133 ,  H05K2201/068 ,  H05K2201/09109 ,  H05K2201/10416 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.

Abstract translation: 具有降低的热膨胀应力的布线基板。 诸如层叠PWB，薄膜电路，引线框架或芯片载体的布线基板可以接受诸如管芯，倒装芯片或球栅阵列封装的集成电路。 布线基板在靠近集成电路的热膨胀应力区域中具有热膨胀应力减小插入件，空隙或构造空隙。 热膨胀应力减小插入物或空隙可以从集成电路连接区域的边缘或边缘延伸选定的距离。 热膨胀应力减小插入物或空隙提高了接合到集成电路的区域中的布线基板的柔性，从而降低了布线基板集成电路组件的部件之间的热应力。 在另一个实施例中，层叠布线基板的层有意地不粘合在芯片附着区域下方，从而允许层压体的上层更大的灵活性。

公开(公告)号：US06299053B1

公开(公告)日：2001-10-09

申请号：US09375172

申请日：1999-08-16

Applicant: Sundar Kamath ,  David Chazan ,  Jan I. Strandberg ,  Solomon I. Beilin

Inventor： Sundar Kamath ,  David Chazan ,  Jan I. Strandberg ,  Solomon I. Beilin

IPC: B23K3102

CPC classification number: H05K1/0271 ,  H01L23/3735 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/0272 ,  H05K2201/0133 ,  H05K2201/068 ,  H05K2201/09109 ,  H05K2201/10416 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.

Abstract translation: 具有降低的热膨胀应力的布线基板。 诸如层叠PWB，薄膜电路，引线框架或芯片载体的布线基板可以接受诸如管芯，倒装芯片或球栅阵列封装的集成电路。 布线基板在靠近集成电路的热膨胀应力区域中具有热膨胀应力减小插入件，空隙或构造空隙。 热膨胀应力减小插入物或空隙可以从集成电路连接区域的边缘或边缘延伸选定的距离。 热膨胀应力减小插入物或空隙提高了接合到集成电路的区域中的布线基板的柔性，从而降低了布线基板集成电路组件的部件之间的热应力。 在另一个实施例中，层叠布线基板的层有意地不粘合在芯片附着区域下方，从而允许层压体的上层更大的灵活性。