公开(公告)号：US06509529B2

公开(公告)日：2003-01-21

申请号：US09960164

申请日：2001-09-20

Applicant: Sundar Kamath ,  David Chazan ,  Jan I. Strandberg ,  Solomon I. Beilin

Inventor： Sundar Kamath ,  David Chazan ,  Jan I. Strandberg ,  Solomon I. Beilin

IPC: H05K103

CPC classification number: H05K1/0271 ,  H01L23/3735 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/0272 ,  H05K2201/0133 ,  H05K2201/068 ,  H05K2201/09109 ,  H05K2201/10416 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.

Abstract translation: 具有降低的热膨胀应力的布线基板。 诸如层叠PWB，薄膜电路，引线框架或芯片载体的布线基板可以接受诸如管芯，倒装芯片或球栅阵列封装的集成电路。 布线基板在靠近集成电路的热膨胀应力区域中具有热膨胀应力减小插入件，空隙或构造空隙。 热膨胀应力减小插入物或空隙可以从集成电路连接区域的边缘或边缘延伸选定的距离。 热膨胀应力减小插入物或空隙提高了接合到集成电路的区域中的布线基板的柔性，从而降低了布线基板集成电路组件的部件之间的热应力。 在另一个实施例中，层叠布线基板的层有意地不粘合在芯片附着区域下方，从而允许层压体的上层更大的灵活性。

公开(公告)号：US06299053B1

公开(公告)日：2001-10-09

申请号：US09375172

申请日：1999-08-16

Applicant: Sundar Kamath ,  David Chazan ,  Jan I. Strandberg ,  Solomon I. Beilin

Inventor： Sundar Kamath ,  David Chazan ,  Jan I. Strandberg ,  Solomon I. Beilin

IPC: B23K3102

CPC classification number: H05K1/0271 ,  H01L23/3735 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/0272 ,  H05K2201/0133 ,  H05K2201/068 ,  H05K2201/09109 ,  H05K2201/10416 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.

Abstract translation: 具有降低的热膨胀应力的布线基板。 诸如层叠PWB，薄膜电路，引线框架或芯片载体的布线基板可以接受诸如管芯，倒装芯片或球栅阵列封装的集成电路。 布线基板在靠近集成电路的热膨胀应力区域中具有热膨胀应力减小插入件，空隙或构造空隙。 热膨胀应力减小插入物或空隙可以从集成电路连接区域的边缘或边缘延伸选定的距离。 热膨胀应力减小插入物或空隙提高了接合到集成电路的区域中的布线基板的柔性，从而降低了布线基板集成电路组件的部件之间的热应力。 在另一个实施例中，层叠布线基板的层有意地不粘合在芯片附着区域下方，从而允许层压体的上层更大的灵活性。

公开(公告)号：US06203967B1

公开(公告)日：2001-03-20

申请号：US09127579

申请日：1998-07-31

Applicant: Scott M. Westbrook ,  Jan I. Strandberg

Inventor： Scott M. Westbrook ,  Jan I. Strandberg

IPC: G03C500

CPC classification number: H05K1/0271 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/0023 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2203/0759 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A method for forming a high density interconnect printed wiring board substrate that has a first patterned conductive layer formed over an upper surface of the substrate that includes multiple conductive lines having edges that define the boundaries of the conductive lines and a dielectric layer formed over the patterned conductive layer and between the edges of the conductive lines. The method includes forming a thin film conductive layer over the dielectric layer, and patterning the thin film conductive layer such that, after the patterning step, the thin film conductive layer overlies each of the edges of the conductive lines. In a preferred embodiment, the thin film conductive layer is patterned such that, after the patterning step, the layer overlies the edges of the conductive lines by at least 10 microns. In another aspect of the invention, a method for strengthening thin film build-up layers deposited over a high density interconnect common circuit base is taught. According to this aspect, a photo-definable thin film dielectric layer having a coefficient of expansion of less than about 10% is formed over a patterned conductive layer, and a thin film conductive layer is formed over the photo-definable thin film dielectric layer. The thin film conductive layer is then patterned to include a plurality of signal lines and a plurality of thieving lines with the thieving lines being placed between nonuniformly spaced signal lines to provide a substantially uniform combined pattern of signal lines and thieving lines.

Abstract translation: 一种用于形成高密度互连印刷线路板基板的方法，其具有形成在所述基板的上表面上的第一图案化导电层，所述第一图案化导电层包括具有限定所述导线的边界的边缘的多个导电线和在所述图案上形成的介电层 导电层和导线的边缘之间。 该方法包括在电介质层上形成薄膜导电层，并对薄膜导电层进行构图，使得在图案化步骤之后，薄膜导电层覆盖在导线的每个边缘上。 在优选实施例中，薄膜导电层被图案化，使得在图案化步骤之后，层覆盖导电线的边缘至少10微米。 在本发明的另一方面，教导了一种用于加强沉积在高密度互连公共电路基底上的薄膜累积层的方法。 根据该方面，在图案化的导电层上形成具有小于约10％的膨胀系数的光可定义薄膜电介质层，并且在可光限定的薄膜电介质层上形成薄膜导电层。 然后，薄膜导电层被图案化以包括多条信号线和多条窃贼线，其中所述窃窃之线被放置在不均匀间隔的信号线之间，以提供信号线和窃盗线的基本均匀的组合图案。

公开(公告)号：US06953999B2

公开(公告)日：2005-10-11

申请号：US11059825

申请日：2005-02-16

Applicant: Jan I. Strandberg ,  Richard Scott Trevino ,  Thomas B. Blount

Inventor： Jan I. Strandberg ,  Richard Scott Trevino ,  Thomas B. Blount

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49822 ,  H01L23/13 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

Abstract: A package for mounting an integrated circuit die. In one embodiment the package comprises a metal substrate having first and second opposing primary surfaces and an aperture formed therebetween. A flexible thin film interconnect structure is formed over the first surface of the metal substrate and over the aperture. The flexible thin film interconnect structure has bottom and top opposing surfaces, a first region that is in direct contact with the first surface of the metal substrate and a second region that is opposite the aperture. The bottom surface of the thin film interconnect structure is in direct contact with the metal substrate in the first region. The thin film interconnect structure comprises (i) a first dielectric layer formed directly on the first surface of the metal substrate and extending over the aperture; (ii) a first metalization layer, formed over the first dielectric layer, comprising a plurality of signal lines positioned over the first region of the thin film interconnect structure and a first plurality of bonding pads positioned over the second region of the thin film interconnect structure; and (iii) a second plurality of bonding pads on the top surface of the thin film interconnect structure. The first plurality of bonding pads have a first pitch appropriate for attaching the integrated circuit die to the package and the second plurality of bonding pads have a pitch greater than the first pitch. Other embodiments of chip level packages as well as various methods for forming such packages are also disclosed.

公开(公告)号：US06440641B1

公开(公告)日：2002-08-27

申请号：US09172178

申请日：1998-10-13

Applicant: James L. Lykins ,  Jan I. Strandberg

Inventor： James L. Lykins ,  Jan I. Strandberg

IPC: G03F700

CPC classification number: H01L23/5385 ,  H01L21/4857 ,  H01L23/5383 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K3/0023 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2203/0759 ,  H05K2203/1476 ,  H01L2924/00

Abstract: The present invention provides a method for controlling the mechanical stresses at the interfaces of the metal and dielectric materials in the printed wiring substrates of high density interconnects. The invention enables the minimization of cracking due to these stresses and does so in an economically attractive process that is able to meet the needs of today's high density interconnect applications. In one embodiment, the method of the present invention dispenses mechanical stresses in a high density interconnect printed wiring board substrate having a first patterned conductive layer formed over an upper surface of the substrate. The patterned conductive layer includes multiple conductive lines each having edges that define the boundaries of the conductive lines. The method of the invention forms a composite dielectric layer over the first patterned conductive layer and between the edges of the conductive layer. The composite dielectric layer includes particles suspended in the layer in order to reduce the likelihood and prevent any cracks that form in the layer from propagating through the entire length of the layer. A thin film conductive layer is then formed over the composite dielectric layer, and a thin film dielectric layer is formed over the thin film conductive layer. In a preferred embodiment, the composite dielectric layer is a CIBA PROBIMER™ layer deposited from a curtain coating process.

Abstract translation: 本发明提供了一种用于控制在高密度互连的印刷布线基板中的金属和介电材料的界面处的机械应力的方法。 本发明能够由于这些应力而最小化裂纹，并且在经济上有吸引力的工艺中能够满足当今高密度互连应用的需要。 在一个实施例中，本发明的方法在具有形成在衬底的上表面上的第一图案化导电层的高密度互连印刷线路板衬底中分配机械应力。 图案化导电层包括多个导线，每个导线具有限定导电线边界的边缘。 本发明的方法在第一图案化导电层之上和导电层的边缘之间形成复合电介质层。 复合介电层包括悬浮在该层中的颗粒，以便降低可能性并防止在层中形成的任何裂纹在层的整个长度上传播。 然后在复合介电层上形成薄膜导电层，并在薄膜导电层上形成薄膜电介质层。 在优选实施例中，复合介电层是从帘式涂布工艺沉积的CIBA PROBIMER TM层。

公开(公告)号：US06323435B1

公开(公告)日：2001-11-27

申请号：US09363959

申请日：1999-07-29

Applicant: Jan I. Strandberg ,  David J. Chazan ,  Michael P. Skinner

Inventor： Jan I. Strandberg ,  David J. Chazan ,  Michael P. Skinner

IPC: H05K103

CPC classification number: H05K1/0271 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/3011 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4673 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2203/0353 ,  H05K2203/0585 ,  H05K2203/0759 ,  H05K2203/1476 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2224/05647

Abstract: Low-impedance high density deposited-on-laminate (DONL) structures having reduced stress features reducing metallization present on the laminate printed circuit board. In this manner, reduced is the force per unit area exerted on the dielectric material disposed adjacent to the laminate material that is typically present during thermal cycling of the structure.

Abstract translation: 具有降低的应力特征的低阻抗高密度叠层（DONL）结构减少层压印刷电路板上存在的金属化。 以这种方式，减小了施加在邻近层压材料设置的电介质材料上的每单位面积的力，其通常在结构的热循环过程中存在。

公开(公告)号：US06872589B2

公开(公告)日：2005-03-29

申请号：US10360845

申请日：2003-02-06

Applicant: Jan I. Strandberg ,  Richard Scott Trevino ,  Thomas B. Blount

Inventor： Jan I. Strandberg ,  Richard Scott Trevino ,  Thomas B. Blount

IPC: H01L23/13 ,  H01L23/498 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/49822 ,  H01L23/13 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

Abstract: A package for mounting an integrated circuit die. In one embodiment the package comprises a metal substrate having first and second opposing primary surfaces and an aperture formed therebetween. A flexible thin film interconnect structure is formed over the first surface of the metal substrate and over the aperture. The flexible thin film interconnect structure has bottom and top opposing surfaces, a first region that is in direct contact with the first surface of the metal substrate and a second region that is opposite the aperture. The bottom surface of the thin film interconnect structure is in direct contact with the metal substrate in the first region. The thin film interconnect structure comprises (i) a first dielectric layer formed directly on the first surface of the metal substrate and extending over the aperture; (ii) a first metalization layer, formed over the first dielectric layer, comprising a plurality of signal lines positioned over the first region of the thin film interconnect structure and a first plurality of bonding pads positioned over the second region of the thin film interconnect structure; and (iii) a second plurality of bonding pads on the top surface of the thin film interconnect structure. The first plurality of bonding pads have a first pitch appropriate for attaching the integrated circuit die to the package and the second plurality of bonding pads have a pitch greater than the first pitch. Other embodiments of chip level packages as well as various methods for forming such packages are also disclosed.

Abstract translation: 用于安装集成电路管芯的封装。 在一个实施例中，包装包括具有第一和第二相对主表面的金属基底和在它们之间形成的孔。 柔性薄膜互连结构形成在金属基板的第一表面上并且在孔之上。 柔性薄膜互连结构具有底部和顶部相对表面，与金属基底的第一表面直接接触的第一区域和与孔相对的第二区域。 薄膜互连结构的底表面与第一区域中的金属基底直接接触。 薄膜互连结构包括（i）直接形成在金属基板的第一表面上并在孔上延伸的第一介电层; （ii）形成在所述第一介电层上的第一金属化层，包括位于所述薄膜互连结构的所述第一区域上方的多个信号线以及位于所述薄膜互连结构的所述第二区域上方的第一多个接合焊盘 ; 和（iii）薄膜互连结构的顶表面上的第二多个接合焊盘。 第一多个接合焊盘具有适于将集成电路管芯附接到封装件的第一间距，并且第二多个接合焊盘具有大于第一间距的间距。 还公开了芯片级封装的其他实施例以及用于形成这种封装的各种方法。

公开(公告)号：US06586682B2

公开(公告)日：2003-07-01

申请号：US09511194

申请日：2000-02-23

Applicant: Jan I. Strandberg

Inventor： Jan I. Strandberg

IPC: H05K103

CPC classification number: H05K3/4602 ,  H05K1/0237 ,  H05K3/0023 ,  H05K3/388 ,  H05K2201/09536 ,  H05K2201/0959

Abstract: The present invention provides a solution to the problem of controlling the inter-layer impedance of a deposited thin film layer stack accommodating high-density interconnects. The invention enables high-density signal lines to be routed over a reference plane to achieve a desired characteristic impedance. In one embodiment, a first thin-film metal layer is formed on a planarized layer fabricated from multiple thin film dielectric layers. The reduced pad footprint in the first thin-film metal layer allows a major portion of the first thin-film metal layer to serve as a reference, or ground, plane to signal lines formed in a second thin-film metal layer that is separated from the first thin-film metal layer by a thin dielectric layer.

公开(公告)号：US6165892A

公开(公告)日：2000-12-26

申请号：US127580

申请日：1998-07-31

Applicant: David J. Chazan ,  Ted T. Chen ,  Todd S. Kaplan ,  James L. Lykins ,  Michael P. Skinner ,  Jan I. Strandberg

Inventor： David J. Chazan ,  Ted T. Chen ,  Todd S. Kaplan ,  James L. Lykins ,  Michael P. Skinner ,  Jan I. Strandberg

IPC: H01L21/48 ,  H01L23/538 ,  H05K1/02 ,  H05K3/00 ,  H05K3/46 ,  H01L21/4763

CPC classification number: H05K3/4673 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0585 ,  H05K2203/0759 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A method for forming a planarized thin film dielectric film on a surface of a common circuit base upon which one or more integrated circuits are to be attached. The common circuit base includes raised features formed over its surface such that the raised features define a trench area between them. The method includes the steps of forming a first layer of the dielectric film over the common circuit base and over the raised features and the trench, then patterning the newly formed layer to remove portions of the layer formed over the raised features and expose the raised features. After the layer is patterned, formation of the dielectric film is completed by forming a second layer of the dielectric film over the patterned first layer. Additional film deposition and film patterning steps are performed to complete the layout of a thin film interconnect structure over said common circuit base, and an integrated circuit die is attached to the common circuit base and electrically connecting to the thin film interconnect structure. In a preferred embodiment, the first and second layers of the dielectric film are both formed from a photo-definable material and the patterning step includes exposing the first layer to light through a patterned mask corresponding to the raised features and developing the exposed layer with a developing solution to etch away portions of the first layer formed over the raised features.

Abstract translation: 一种用于在公共电路基底的表面上形成平坦化的薄膜电介质膜的方法，一个或多个集成电路将安装在该公共电路基底上。 公共电路基座包括在其表面上形成的凸起特征，使得凸起特征在它们之间限定沟槽区域。 该方法包括以下步骤：在公共电路基底上方和凸起的特征​​和沟槽上形成电介质膜的第一层，然后对新形成的层进行图案化以去除在凸起特征上形成的层的部分，并暴露凸起特征 。 在层被图案化之后，通过在图案化的第一层上形成电介质膜的第二层来完成电介质膜的形成。 执行附加的膜沉积和膜图案化步骤以在所述公共电路基底上完成薄膜互连结构的布局，并且集成电路管芯附接到公共电路基座并电连接到薄膜互连结构。 在优选实施例中，电介质膜的第一和第二层都由光可定义材料形成，并且图案化步骤包括通过对应于凸起特征的图案化掩模将第一层暴露于光，并将曝光层用 显影溶液以蚀刻形成在凸起特征上的第一层的部分。