公开(公告)号：US11481250B2

公开(公告)日：2022-10-25

申请号：US16024244

申请日：2018-06-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexandru Dutu ,  Matthew David Sinclair ,  Bradford Beckmann ,  David A. Wood

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F9/52

Abstract: A first workgroup is preempted in response to threads in the first workgroup executing a first wait instruction including a first value of a signal and a first hint indicating a type of modification for the signal. The first workgroup is scheduled for execution on a processor core based on a first context after preemption in response to the signal having the first value. A second workgroup is scheduled for execution on the processor core based on a second context in response to preempting the first workgroup and in response to the signal having a second value. A third context it is prefetched into registers of the processor core based on the first hint and the second value. The first context is stored in a first portion of the registers and the second context is prefetched into a second portion of the registers prior to preempting the first workgroup.

公开(公告)号：US20170371784A1

公开(公告)日：2017-12-28

申请号：US15192542

申请日：2016-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan R. Alsop ,  Bradford Beckmann

IPC: G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/0897

CPC classification number: G06F12/0897 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0891 ,  G06F2212/6042

Abstract: A processing system includes one or more first caches and one or more first lock tables associated with the one or more first caches. The processing system also includes one or more processing units that each include a plurality of compute units for concurrently executing work-groups of work items, a plurality of second caches associated with the plurality of compute units and configured in a hierarchy with the one or more first caches, and a plurality of second lock tables associated with the plurality of second caches. The first and second lock tables indicate locking states of addresses of cache lines in the corresponding first and second caches on a per-line basis.

公开(公告)号：US20250123846A1

公开(公告)日：2025-04-17

申请号：US18485502

申请日：2023-10-12

Applicant: Advanced Micro Devices, Inc.

Inventor： William Peter Ehrett ,  Muhammad Osama ,  Bradford Beckmann

IPC: G06F9/38

Abstract: A processing unit includes a plurality of processing cores and is configured to arrange a sparse matrix for parallel performance by the cores on different rows of the matrix at least in part by calculating a respective quantity of non-zero elements in each row, assigning each row to a respective collection according to the respective quantity of non-zero elements for the row, wherein the processing unit is configured to assign at least one first row of the sparse matrix to respective collections of in parallel with assigning at least one second row of the sparse matrix to respective collections, and performing at least one mathematical operation on at least a first collection of the plurality of collections in parallel with performing the at least one mathematical operation on at least a second collection of the plurality of collections.

公开(公告)号：US20240095180A1

公开(公告)日：2024-03-21

申请号：US18088170

申请日：2022-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Michael Estlick ,  Jay Fleischman ,  Michael J. Schulte ,  Bradford Beckmann ,  Yasuko Eckert

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/1008

Abstract: The disclosed computer-implemented method for interpolating register-based lookup tables can include identifying, within a set of registers, a lookup table that has been encoded for storage within the set of registers. The method can also include receiving a request to look up a value in the lookup table and responding to the request by interpolating, from the encoded lookup table stored in the set of registers, a representation of the requested value. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11868809B2

公开(公告)日：2024-01-09

申请号：US18095704

申请日：2023-01-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Muhammad Amber Hassaan ,  Anirudh Mohan Kaushik ,  Sooraj Puthoor ,  Gokul Subramanian Ravi ,  Bradford Beckmann ,  Ashwin Aji

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/52 ,  G06F16/901

CPC classification number: G06F9/4881 ,  G06F9/52 ,  G06F16/9024 ,  G06F2209/486

Abstract: A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.

公开(公告)号：US11526449B2

公开(公告)日：2022-12-13

申请号：US17007133

申请日：2020-08-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Johnathan Alsop ,  Pouya Fotouhi ,  Bradford Beckmann ,  Sergey Blagodurov

IPC: G06F12/08 ,  G06F12/0891 ,  G06F9/30 ,  G06F12/0882 ,  G06F12/0811

Abstract: A processing system limits the propagation of unnecessary memory updates by bypassing writing back dirty cache lines to other levels of a memory hierarchy in response to receiving an indication from software executing at a processor of the processing system that the value of the dirty cache line is dead (i.e., will not be read again or will not be read until after it has been overwritten). In response to receiving an indication from software that data is dead, a cache controller prevents propagation of the dead data to other levels of memory in response to eviction of the dead data or flushing of the cache at which the dead data is stored.

公开(公告)号：US20250103395A1

公开(公告)日：2025-03-27

申请号：US18476071

申请日：2023-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Bradford Beckmann ,  Matthew David Sinclair ,  Vinay Bharadwaj Ramakrishnaiah ,  William Peter Ehrett

IPC: G06F9/50

Abstract: A computer-implemented method for dynamic resource management can include evaluating, by at least one processor, whether a priority of one or more processes associated with a request for one or more shared resources meets a threshold condition. The method can additionally include determining, by the at least one processor and in response to an evaluation that the priority meets the threshold condition, whether the one or more shared resources is available to meet the request. The method can further include completing, by the at least one processor and in response to a determination that the one or more shared resources is available, execution of the one or more processes. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US10409610B2

公开(公告)日：2019-09-10

申请号：US15010093

申请日：2016-01-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Bradford Beckmann ,  Sooraj Puthoor

IPC: G06F9/38 ,  G06F9/48

Abstract: Briefly, methods and apparatus to migrate a software thread from one wavefront executing on one execution unit to another wavefront executing on another execution unit whereby both execution units are associated with a compute unit of a processing device such as, for example, a GPU. The methods and apparatus may execute compiled dynamic thread migration swizzle buffer instructions that when executed allow access to a dynamic thread migration swizzle buffer that allows for the migration of register context information when migrating software threads. The register context information may be located in one or more locations of a register file prior to storing the register context information into the dynamic thread migration swizzle buffer. The method and apparatus may also return the register context information from the dynamic thread migration swizzle buffer to one or more different register file locations of the register file.

公开(公告)号：US20150106587A1

公开(公告)日：2015-04-16

申请号：US14055221

申请日：2013-10-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Shuai Che ,  Bradford Beckmann ,  Blake Hechtman

IPC: G06F12/10

CPC classification number: G06F12/1054 ,  G06F12/0207 ,  G06F12/0284 ,  G06F12/10 ,  G06F12/109 ,  G06F2212/251

Abstract: A processor remaps stored data and the corresponding memory addresses of the data for different processing units of a heterogeneous processor. The processor includes a data remap engine that changes the format of the data (that is, how the data is physically arranged in segments of memory) in response to a transfer of the data from system memory to a local memory hierarchy of an accelerated processing module (APM) of the processor. The APM's local memory hierarchy includes an address remap engine that remaps the memory addresses of the data at the local memory hierarchy so that the data can be accessed by routines at the APM that are unaware of the data remapping. By remapping the data, and the corresponding memory addresses, the APM can perform operations on the data more efficiently.

Abstract translation: 处理器重新映射异构处理器的不同处理单元的存储数据和相应的数据存储器地址。 处理器包括响应于数据从系统存储器传输到加速处理模块的本地存储器层级而改变数据格式（即，数据在存储器段中物理布置的方式）的数据重映射引擎 （APM）。 APM的本地存储器层次结构包括地址重映射引擎，其重映射本地存储器层级上的数据的存储器地址，使得可以通过APM的不知道数据重映射的例程来访问数据。 通过重新映射数据和相应的存储器地址，APM可以更有效地对数据执行操作。

公开(公告)号：US12299445B2

公开(公告)日：2025-05-13

申请号：US17833504

申请日：2022-06-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Yasuko Eckert ,  Bradford Beckmann ,  Michael Estlick ,  Jay Fleischman

IPC: G06F9/30

Abstract: An approach is provided for implementing register based single instruction, multiple data (SIMD) lookup table operations. According to the approach, an instruction set architecture (ISA) can support one or more SIMD instructions that enable vectors or multiple values in source data registers to be processed in parallel using a lookup table or truth table stored in one or more function registers. The SIMD instructions can be flexibly configured to support functions with inputs and outputs of various sizes and data formats. Various approaches are also described for supporting very large lookup tables that span multiple registers.