中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

24 records (took 0.016 seconds)

    System probe aware last level cache insertion bypassing
    1.
    发明授权
    System probe aware last level cache insertion bypassing 有权

    公开(公告)号：US11163688B2

    公开(公告)日：2021-11-02

    申请号：US16580139

    申请日：2019-09-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Paul James Moyer ,  Jay Fleischman

    IPC: G06F12/0888 ,  G06F12/0811 ,  G06F12/0846

    Abstract: Systems, apparatuses, and methods for employing system probe filter aware last level cache insertion bypassing policies are disclosed. A system includes a plurality of processing nodes, a probe filter, and a shared cache. The probe filter monitors a rate of recall probes that are generated, and if the rate is greater than a first threshold, then the system initiates a cache partitioning and monitoring phase for the shared cache. Accordingly, the cache is partitioned into two portions. If the hit rate of a first portion is greater than a second threshold, then a second portion will have a non-bypass insertion policy since the cache is relatively useful in this scenario. However, if the hit rate of the first portion is less than or equal to the second threshold, then the second portion will have a bypass insertion policy since the cache is less useful in this case.

    SYSTEM PROBE AWARE LAST LEVEL CACHE INSERTION BYPASSING
    2.
    发明申请
    SYSTEM PROBE AWARE LAST LEVEL CACHE INSERTION BYPASSING 有权

    公开(公告)号：US20210089462A1

    公开(公告)日：2021-03-25

    申请号：US16580139

    申请日：2019-09-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Paul James Moyer ,  Jay Fleischman

    IPC: G06F12/0888 ,  G06F12/0846 ,  G06F12/0811

    Abstract: Systems, apparatuses, and methods for employing system probe filter aware last level cache insertion bypassing policies are disclosed. A system includes a plurality of processing nodes, a probe filter, and a shared cache. The probe filter monitors a rate of recall probes that are generated, and if the rate is greater than a first threshold, then the system initiates a cache partitioning and monitoring phase for the shared cache. Accordingly, the cache is partitioned into two portions. If the hit rate of a first portion is greater than a second threshold, then a second portion will have a non-bypass insertion policy since the cache is relatively useful in this scenario. However, if the hit rate of the first portion is less than or equal to the second threshold, then the second portion will have a bypass insertion policy since the cache is less useful in this case.

    Accelerated reversal of speculative state changes and resource recovery
    3.
    发明授权
    Accelerated reversal of speculative state changes and resource recovery 有权
    加速逆转投机状态变化和资源回收

    公开(公告)号：US09575763B2

    公开(公告)日：2017-02-21

    申请号：US13918863

    申请日：2013-06-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jay Fleischman ,  Michael Estlick

    IPC: G06F9/32 ,  G06F9/38

    CPC classification number: G06F9/384 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3861

    Abstract: A method includes undoing, in reverse program order, changes in a state of a processing device caused by speculative instructions previously dispatched for execution in the processing device and concurrently deallocating resources previously allocated to the speculative instructions in response to interruption of dispatch of instructions due to a flush of the speculative instructions. A processor device comprises a retire queue to store entries for instructions that are awaiting retirement and a finite state machine. The finite state machine is to interrupt dispatch of instructions in response to a flush of speculative instructions previously dispatched for execution in the processing device and to undo, in reverse program order, changes in a state of the processing device caused by the speculative instructions while concurrently deallocating resources previously allocated to the speculative instructions.

    Abstract translation: 一种方法包括以反向程序顺序来撤销由先前在处理设备中执行的推测性指令引起的处理设备的状态的改变，并且响应于由于指令的发送中断而先前分配给推测指令的资源 冲突的投机指示。 处理器设备包括用于存储等待退休的指令的条目的退出队列和有限状态机。 有限状态机是响应于先前调度以在处理设备中执行的推测性指令的刷新来中断指令的分派，并且以反向程序顺序撤销由推测指令引起的处理设备的状态的改变，同时 释放以前分配给投机指示的资源。

    MECHANISM FOR RESOURCE UTILIZATION METERING IN A COMPUTER SYSTEM
    4.
    发明申请
    MECHANISM FOR RESOURCE UTILIZATION METERING IN A COMPUTER SYSTEM 审中-公开
    计算机系统资源利用计量的机制

    公开(公告)号：US20170031719A1

    公开(公告)日：2017-02-02

    申请号：US15097859

    申请日：2016-04-13

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Michael T. Clark ,  Jay Fleischman ,  Thaddeus S. Fortenberry ,  Maurice B. Steinman

    IPC: G06F9/50 ,  G06F9/455 ,  G06F12/08

    CPC classification number: G06F9/5016 ,  G06F9/45558 ,  G06F9/5077 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F12/121 ,  G06F2009/4557 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2209/501 ,  G06F2209/508 ,  G06F2212/1041 ,  G06F2212/152 ,  G06F2212/283

    Abstract: Systems, apparatuses, and methods for tracking system resource utilization of guest virtual machines (VMs). Counters may be maintained to track resource utilization of different system resources by different guest VMs executing on the system. When a guest VM initiates execution, stored values may be loaded into the resource utilization counters. While the guest VM executes, the counters may track the resource utilization of the guest VM. When the guest VM terminates execution, the counter values may be written to a virtual machine control block (VMCB) corresponding to the guest VM. Scaling factors may be applied to the counter values to normalize the values prior to writing the values to the VMCB. A cloud computing environment may utilize the tracking mechanisms to guarantee resource utilization levels in accordance with users' service level agreements.

    Abstract translation: 用于跟踪来宾虚拟机（VM）的系统资源利用的系统，设备和方法。 可以维护计数器以跟踪在系统上执行的不同来宾VM的不同系统资源的资源利用。 当guest虚拟机启动执行时，存储的值可能被加载到资源利用率计数器中。 客机虚拟机执行时，计数器可以跟踪来宾虚拟机的资源利用率。 当客人VM终止执行时，可以将计数器值写入到与虚拟机对应的虚拟机控制块（VMCB）。 缩放因子可以应用于计数器值，以便在将值写入VMCB之前规范化值。 云计算环境可以利用跟踪机制来根据用户的服务水平协议来保证资源利用水平。

    System probe aware last level cache insertion bypassing
    5.
    发明授权
    System probe aware last level cache insertion bypassing 有权

    公开(公告)号：US12204454B2

    公开(公告)日：2025-01-21

    申请号：US17514417

    申请日：2021-10-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Paul James Moyer ,  Jay Fleischman

    IPC: G06F12/0888 ,  G06F12/0811 ,  G06F12/0846

    Abstract: Systems, apparatuses, and methods for employing system probe filter aware last level cache insertion bypassing policies are disclosed. A system includes a plurality of processing nodes, a probe filter, and a shared cache. The probe filter monitors a rate of recall probes that are generated, and if the rate is greater than a first threshold, then the system initiates a cache partitioning and monitoring phase for the shared cache. Accordingly, the cache is partitioned into two portions. If the hit rate of a first portion is greater than a second threshold, then a second portion will have a non-bypass insertion policy since the cache is relatively useful in this scenario. However, if the hit rate of the first portion is less than or equal to the second threshold, then the second portion will have a bypass insertion policy since the cache is less useful in this case.

    ACCELERATED REVERSAL OF SPECULATIVE STATE CHANGES AND RESOURCE RECOVERY
    8.
    发明申请
    ACCELERATED REVERSAL OF SPECULATIVE STATE CHANGES AND RESOURCE RECOVERY 有权
    调整状态变化和资源恢复的加速反转

    公开(公告)号：US20140372732A1

    公开(公告)日：2014-12-18

    申请号：US13918863

    申请日：2013-06-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jay Fleischman ,  Michael Estlick

    IPC: G06F9/38

    CPC classification number: G06F9/384 ,  G06F9/3842 ,  G06F9/3859 ,  G06F9/3861

    Abstract: A method includes undoing, in reverse program order, changes in a state of a processing device caused by speculative instructions previously dispatched for execution in the processing device and concurrently deallocating resources previously allocated to the speculative instructions in response to interruption of dispatch of instructions due to a flush of the speculative instructions. A processor device comprises a retire queue to store entries for instructions that are awaiting retirement and a finite state machine. The finite state machine is to interrupt dispatch of instructions in response to a flush of speculative instructions previously dispatched for execution in the processing device and to undo, in reverse program order, changes in a state of the processing device caused by the speculative instructions while concurrently deallocating resources previously allocated to the speculative instructions.

    Abstract translation: 一种方法包括以反向程序顺序来撤销由先前在处理设备中执行的推测性指令引起的处理设备的状态的改变，并且响应于由于指令的发送中断而先前分配给推测指令的资源 冲突的投机指示。 处理器设备包括用于存储等待退休的指令的条目的退出队列和有限状态机。 有限状态机是响应于先前调度以在处理设备中执行的推测性指令的刷新来中断指令的分派，并且以反向程序顺序撤销由推测指令引起的处理设备的状态的改变，同时 释放以前分配给投机指示的资源。

    LARGE NUMBER INTEGER ADDITION USING VECTOR ACCUMULATION
    10.
    发明公开
    LARGE NUMBER INTEGER ADDITION USING VECTOR ACCUMULATION 审中-公开

    公开(公告)号：US20240319964A1

    公开(公告)日：2024-09-26

    申请号：US18126107

    申请日：2023-03-24

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Onur Kayiran ,  Lee Evan Eisen ,  Michael Estlick ,  Jay Fleischman ,  Matthew R. Poremba ,  Gabriel H. Loh

    IPC: G06F7/503

    CPC classification number: G06F7/503

    Abstract: A processor includes one or more processor cores configured to perform accumulate top (ACCT) and accumulate bottom (ACCB) instructions. To perform such instructions, at least one processor core of the processor includes an ACCT data path that adds a first portion of a block of data to a first lane of a set of lanes of a top accumulator and adds a carry-out bit to a second lane of the set of lanes of the top accumulator. Further, the at least one processor core includes an ACCB data path that adds a second portion of the block of data to a first lane of a set of lanes of a bottom accumulator and adds a carry-out bit to a second lane of the set of lanes of the bottom accumulator.

Patent Agency Ranking