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公开(公告)号：US20250072045A1
公开(公告)日：2025-02-27
申请号：US18455611
申请日：2023-08-24
Inventor： Sik Lui , Madhur Bobde , Wenwen Li , Xiaobin Wang , Lingpeng Guan
IPC: H01L29/78 , H01L29/06 , H01L29/66 , H02J7/00 , H03K17/0812
Abstract: A trench MOSFET device implements a trench source/body contact structure and includes a first MOSFET section and a second MOSFET section where the first MOSFET section has a body contact resistance lower than a body contact resistance of the second MOSFET section. In some embodiments, the first MOSFET section includes trench source/body contacts to make electrical contact with the source region and with a body contact doped region having a first doping level. In one embodiment, the second MOSFET section includes trench source/body contacts that contacts only the source region. In another embodiment, the second MOSFET section includes trench source/body contacts to make electrical contact with the source region and with a second body contact doped region having a second doping level lower than the first doping level. In some embodiments, the first MOSFET section has a transistor area much smaller than the transistor area of the second MOSFET section.
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公开(公告)号：US20230238440A1
公开(公告)日：2023-07-27
申请号：US17581796
申请日：2022-01-21
Inventor： Madhur Bobde , Sik Lui , Lei Zhang , Xiaobin Wang
IPC: H01L29/423 , H01L29/10 , H01L21/8234
CPC classification number: H01L29/4236 , H01L29/1095 , H01L21/823462
Abstract: A device and a method of making the device comprising, a semiconductor substrate layer and an epitaxial layer formed on the semiconductor substrate. One or more trenches are formed in the epitaxial layer, each trench having a pair of opposing sidewalls, wherein a distance between the opposing sidewalls is greater near a bottom of the trench than near a top of the trench, wherein the bottom of the trench is closer to the semiconductor substrate layer than the top.
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公开(公告)号：US20250157894A1
公开(公告)日：2025-05-15
申请号：US18758522
申请日：2024-06-28
Inventor： Yan Xun Xue , Jian Yin , Long-Ching Wang , Sitthipong Angkititrakul , Xiaobin Wang , Bo Chen
IPC: H01L23/495 , H01L23/00 , H01L23/31 , H01L25/00 , H01L25/065 , H01L29/772
Abstract: A semiconductor package comprises a lead frame, a first field-effect transistor (FET), a second FET, an integrated circuit (IC), a plurality of bond wires, and a molding encapsulation. The lead frame comprises a first die paddle and a second die paddle. The first FET is flipped and attached to the first die paddle. The second FET is flipped and attached to the second die paddle. A method comprises the steps of providing a lead frame comprising a first die paddle and a second die paddle; applying a first adhesive layer; mounting a first FET and a second FET; applying a second adhesive layer; mounting an IC; applying bonding wires; forming a molding encapsulation; and applying a singulation process so as to form a plurality of semiconductor packages.
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Patent Agency Ranking
公开(公告)号：US12295166B2
公开(公告)日：2025-05-06
申请号：US17581796
申请日：2022-01-21
Inventor： Madhur Bobde , Sik Lui , Lei Zhang , Xiaobin Wang
IPC: H01L29/423 , H10D62/17 , H10D64/27 , H10D84/01 , H10D84/03
Abstract: A device and a method of making the device comprising, a semiconductor substrate layer and an epitaxial layer formed on the semiconductor substrate. One or more trenches are formed in the epitaxial layer, each trench having a pair of opposing sidewalls, wherein a distance between the opposing sidewalls is greater near a bottom of the trench than near a top of the trench, wherein the bottom of the trench is closer to the semiconductor substrate layer than the top.
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公开(公告)号：US20250081517A1
公开(公告)日：2025-03-06
申请号：US18241783
申请日：2023-09-01
Inventor： Wenwen Li , Xiaobin Wang , Sik Lui , Adithya Prakash , Lingpeng Guan , Madhur Bobde
Abstract: A multiple gate transistor and method of its manufacture are described. The transistor comprises a common substrate, a source, a drain, a body, a first gate electrode and a second gate electrode. The first gate electrode and the second gate electrode are colinearly aligned along a horizontal plane of the common substrate and are separated by a dielectric wall. The dielectric wall provides electrical isolation between the first gate electrode and the second gate electrode.
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公开(公告)号：US11774296B2
公开(公告)日：2023-10-03
申请号：US17524566
申请日：2021-11-11
Inventor： Zhenyu Wang , Jian Yin , Lingpeng Guan , Sitthipong Angkititrakul , Christopher Ben Bartholomeusz , Xiaobin Wang
Abstract: A method and device for temperature monitoring of a power transistor formed in a semiconductor die comprising are disclosed. A side of a temperature-sensing resistor disposed in the semiconductor die is coupled to a voltage input side of the power transistor. A controller coupled to a second side of the temperature-sensing resistor is configured to detect a voltage across the resistor and trigger a temperature related corrective action using the detected voltage.
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公开(公告)号：US20230147081A1
公开(公告)日：2023-05-11
申请号：US17524566
申请日：2021-11-11
Inventor： Zhenyu Wang , Jian Yin , Lingpeng Guan , Sitthipong Angkititrakul , Christopher Ben Bartholomeusz , Xiaobin Wang
Abstract: A method and device for temperature monitoring of a power transistor formed in a semiconductor die comprising are disclosed. A side of a temperature-sensing resistor disposed in the semiconductor die is coupled to a voltage input side of the power transistor. A controller coupled to a second side of the temperature-sensing resistor is configured to detect a voltage across the resistor and trigger a temperature related corrective action using the detected voltage.
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公开(公告)号：US20250118638A1
公开(公告)日：2025-04-10
申请号：US18378503
申请日：2023-10-10
Inventor： Yan Xun Xue , Madhur Bobde , Long-Ching Wang , Jian Yin , Lin Chen , Ziwei Yu , Xiaobin Wang , Zhiqiang Niu , Kuan-Hung Li
IPC: H01L23/495 , H01L23/00 , H01L23/31
Abstract: A semiconductor package comprises a first device and a second device. The structure of the first semiconductor device is similar to that of the second semiconductor device. The first semiconductor device comprises a lead frame strip, a first plurality of field effect transistors (FETs), a first plurality of clips, a second plurality of FETs, a second plurality of clips, and a first molding encapsulation. A method is applied to fabricate a plurality of semiconductor packages. The method comprises the steps of providing a lead frame strip, attaching a first plurality of FETs, attaching a first plurality of clips, attaching a second plurality of FETs, attaching a second plurality of clips, and forming a molding encapsulation.
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