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公开(公告)号：US20230412070A1
公开(公告)日：2023-12-21
申请号：US18241836
申请日：2023-09-01
Inventor： Ziwei Yu , Lin Chen , Zhiqiang Niu
CPC classification number: H02M1/44 , H05K7/209 , H05K1/181 , H05K1/111 , H05K2201/10166
Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.
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公开(公告)号：US20250118638A1
公开(公告)日：2025-04-10
申请号：US18378503
申请日：2023-10-10
Inventor： Yan Xun Xue , Madhur Bobde , Long-Ching Wang , Jian Yin , Lin Chen , Ziwei Yu , Xiaobin Wang , Zhiqiang Niu , Kuan-Hung Li
IPC: H01L23/495 , H01L23/00 , H01L23/31
Abstract: A semiconductor package comprises a first device and a second device. The structure of the first semiconductor device is similar to that of the second semiconductor device. The first semiconductor device comprises a lead frame strip, a first plurality of field effect transistors (FETs), a first plurality of clips, a second plurality of FETs, a second plurality of clips, and a first molding encapsulation. A method is applied to fabricate a plurality of semiconductor packages. The method comprises the steps of providing a lead frame strip, attaching a first plurality of FETs, attaching a first plurality of clips, attaching a second plurality of FETs, attaching a second plurality of clips, and forming a molding encapsulation.
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公开(公告)号：US11750089B2
公开(公告)日：2023-09-05
申请号：US17513341
申请日：2021-10-28
Inventor： Ziwei Yu , Lin Chen , Zhiqiang Niu
CPC classification number: H02M1/44 , H05K1/111 , H05K1/181 , H05K7/209 , H05K2201/10166
Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.
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Patent Agency Ranking
公开(公告)号：US12160196B2
公开(公告)日：2024-12-03
申请号：US18049969
申请日：2022-10-26
Inventor： ChengYuan He , Sitthipong Angkititraku , Jian Yin , Lin Chen
IPC: G01R19/165 , H02P6/28 , H02P27/08 , H02K7/14
Abstract: Apparatus and associated methods relate to a Source Terminal Replication Compensation Circuit for simulating an accurate fraction of a load current. In an illustrative example, a Source Terminal Replication Compensation Circuit (STRCC) may be connected to a motor driving circuit. The STRCC, for example, may include a simulation transistor configured to have a simulated structure of a main transistor in a motor driving circuit. The STRCC may include, for example, a disturbance rejection module (DRM). The DRM may be connected to a source terminal of the sense transistor, and a source terminal of the main transistor. When the DRM is connected to a current sensing resistor, a sense current is generated as a predetermined fraction of a load current of the motor driving circuit, wherein the predetermined fraction is less than 1%. Various embodiments may advantageously reduce heat dissipations at the current sensor resistor.
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公开(公告)号：US20240146218A1
公开(公告)日：2024-05-02
申请号：US18049969
申请日：2022-10-26
Inventor： ChengYuan He , Sitthipong Angkititraku , Jian Yin , Lin Chen
Abstract: Apparatus and associated methods relate to a Source Terminal Replication Compensation Circuit for simulating an accurate fraction of a load current. In an illustrative example, a Source Terminal Replication Compensation Circuit (STRCC) may be connected to a motor driving circuit. The STRCC, for example, may include a simulation transistor configured to have a simulated structure of a main transistor in a motor driving circuit. The STRCC may include, for example, a disturbance rejection module (DRM). The DRM may be connected to a source terminal of the sense transistor, and a source terminal of the main transistor. When the DRM is connected to a current sensing resistor, a sense current is generated as a predetermined fraction of a load current of the motor driving circuit, wherein the predetermined fraction is less than 1%. Various embodiments may advantageously reduce heat dissipations at the current sensor resistor.
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公开(公告)号：US20240096768A1
公开(公告)日：2024-03-21
申请号：US17946992
申请日：2022-09-16
Inventor： Yan Xun Xue , Lin Chen , Long-Ching Wang , Hui Ye
IPC: H01L23/495 , H01L23/00 , H01L23/31
CPC classification number: H01L23/49575 , H01L23/3107 , H01L23/49517 , H01L23/49548 , H01L23/49562 , H01L24/40 , H01L2224/40137
Abstract: A semiconductor package includes a lead frame, a low side field-effect transistor (FET), a high side FET, a metal clip, and a molding encapsulation. The low side FET is flipped and is attached to a first die paddle of the lead frame. The lead frame comprises one or more voltage input (Vin) leads; a gate lead; one or more switching node (Lx) leads; a first die paddle; a second die paddle; and an end paddle. Each of an exposed bottom surface of the one or more Lx leads is directly connected to an exposed bottom surface of the end paddle. A longitudinal direction of an exposed bottom surface of the gate lead is perpendicular to a longitudinal direction of each of the exposed bottom surface of the one or more Lx leads. An entirely of each of the one or more Vin leads is of the full thickness.
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公开(公告)号：US12015336B2
公开(公告)日：2024-06-18
申请号：US18241836
申请日：2023-09-01
Inventor： Ziwei Yu , Lin Chen , Zhiqiang Niu
CPC classification number: H02M1/44 , H05K1/111 , H05K1/181 , H05K7/209 , H05K2201/10166
Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.
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公开(公告)号：US20230137176A1
公开(公告)日：2023-05-04
申请号：US17513341
申请日：2021-10-28
Inventor： Ziwei Yu , Lin Chen , Zhiqiang Niu
Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.
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