公开(公告)号：US20170350937A1

公开(公告)日：2017-12-07

申请号：US15685516

申请日：2017-08-24

Applicant: Altera Corporation

Inventor： Wai Tat Wong ,  Edwin Yew Fatt Kok ,  Wilfred Wee Kee King ,  Tee Wee Tan

IPC: G01R31/28

CPC classification number: G01R31/2851 ,  H03K19/17764

Abstract: In one embodiment, an integrated circuit is disclosed. The integrated includes a general purpose processor, an interface circuit, and a calibration adapter circuit. The general purpose processor circuit generates calibration test inputs based on user instruction. The analog interface circuit may include a calibration bus circuit. The calibration bus circuit may receive the calibration test input from the general purpose processor circuit. The calibration adapter circuit is coupled to the calibration bus circuit and the general purpose processor circuit and transmits the calibration test inputs to the calibration bus circuit.

公开(公告)号：US10218360B2

公开(公告)日：2019-02-26

申请号：US15226037

申请日：2016-08-02

Applicant: Altera Corporation

Inventor： Dinesh Patil ,  Kok Hong Chan ,  Wai Tat Wong ,  Chuan Thim Khor

IPC: H03K19/177 ,  G06F1/04 ,  H03L7/08 ,  H03L7/081 ,  H04L12/875 ,  G06F1/12 ,  G11C7/22

Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

公开(公告)号：US10439615B2

公开(公告)日：2019-10-08

申请号：US16246629

申请日：2019-01-14

Applicant: Altera Corporation

Inventor： Dinesh Patil ,  Kok Hong Chan ,  Wai Tat Wong ,  Chuan Thim Khor

IPC: H03K19/177 ,  G06F1/04 ,  H03L7/08 ,  H03L7/081 ,  H04L12/875 ,  G06F1/12 ,  G11C7/22

Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

公开(公告)号：US20180041328A1

公开(公告)日：2018-02-08

申请号：US15226037

申请日：2016-08-02

Applicant: Altera Corporation

Inventor： Dinesh Patil ,  Kok Hong Chan ,  Wai Tat Wong ,  Chuan Thim Khor

IPC: H04L7/00 ,  H03K19/177 ,  H04L12/863 ,  H03L7/08

CPC classification number: H03K19/1776 ,  G06F1/04 ,  G06F1/12 ,  G11C7/222 ,  H03K19/17728 ,  H03L7/0805 ,  H03L7/0814 ,  H04L47/56

Abstract: The present embodiments relate to clock-data phase alignment circuitry in source-synchronous interface circuits. Source-synchronous interface standards require the transmission and reception of a clock signal that is transmitted separately from the data signal. On the receiver side, the clock signal must be phase shifted relative to the data signal to enable the capture of the data. Clock-data phase alignment circuitry is presented that may receive a differential clock with complementary clock signals CLK_P and CLK_N. An adjustable delay circuit and clock distribution network may delay clock signal CLK_P and provide the delayed clock signal to a storage circuit that may store the data signal. A replica clock distribution network and a replica adjustable delay circuit may form a feedback path and provide the delayed first clock signal back to clock phase adjustment circuitry which may control the adjustment of the adjustable delay circuit and the replica adjustable delay circuit.

公开(公告)号：US09778312B1

公开(公告)日：2017-10-03

申请号：US14055459

申请日：2013-10-16

Applicant: Altera Corporation

Inventor： Wai Tat Wong ,  Edwin Yew Fatt Kok ,  Wilfred Wee Kee King ,  Tee Wee Tan

IPC: G01R31/28

CPC classification number: G01R31/2851 ,  H03K19/17764

Abstract: In one embodiment, an integrated circuit is disclosed. The integrated includes a general purpose processor, an interface circuit, and a calibration adapter circuit. The general purpose processor circuit generates calibration test inputs based on user instruction. The analog interface circuit may include a calibration bus circuit. The calibration bus circuit may receive the calibration test input from the general purpose processor circuit. The calibration adapter circuit is coupled to the calibration bus circuit and the general purpose processor circuit and transmits the calibration test inputs to the calibration bus circuit.

公开(公告)号：US09237001B1

公开(公告)日：2016-01-12

申请号：US14159248

申请日：2014-01-20

Applicant: ALTERA CORPORATION

Inventor： Ting Lok Song ,  Wai Tat Wong

IPC: H04B3/46 ,  H04B17/00 ,  H04Q1/20 ,  H04L7/00

CPC classification number: H04L7/0016 ,  G06F1/10 ,  H03K5/1565 ,  H03K7/08 ,  H03M9/00 ,  H04L25/03 ,  H04L25/05 ,  H04L25/14

Abstract: One embodiment relates to a method of calibrating duty cycle distortion. A data rate of a physical layer interface is changed from a lower rate to a higher rate, and a data rate of one or more transceivers associated with the physical layer interface is changed from the lower rate to the higher rate. An electrical idle state is maintained after changing the data rate of the transceiver. Duty cycle distortion calibration for one or more transceivers associated with the physical layer interface is then performed during the electrical idle state. Other embodiments and features are also disclosed.

Abstract translation: 一个实施例涉及校准占空比失真的方法。 物理层接口的数据速率从较低速率变化到较高速率，并且与物理层接口相关联的一个或多个收发器的数据速率从较低速率变为较高速率。 在更改收发器的数据速率后，保持电气空闲状态。 然后在电气空闲状态期间执行与物理层接口相关联的一个或多个收发器的占空比失真校准。 还公开了其它实施例和特征。