公开(公告)号：US09631481B1

公开(公告)日：2017-04-25

申请号：US15293524

申请日：2016-10-14

Applicant: AMKOR TECHNOLOGY, INC.

Inventor： Jae Min Bae ,  Byong Jin Kim ,  Won Bae Bang

IPC: H01L33/62 ,  E21B47/10 ,  G01N29/024 ,  E21B49/00 ,  E21B21/08

CPC classification number: H01L23/564 ,  C08G77/14 ,  C08L83/06 ,  C08L2205/025 ,  E21B21/08 ,  E21B47/101 ,  E21B49/005 ,  G01N29/024 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49548 ,  H01L33/56 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/181 ,  C08L83/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a die pad, a plurality of first lands each having a first land first top recessed portion disposed on a first land first end distal to the die pad, and a plurality of second lands each having a second land first bottom recessed portion disposed on a second land first end distal to the die pad. A semiconductor die is electrically connected to the first and second lands. A package body, which defines a bottom surface and a side surface, at least partially encapsulating the first and second lands and the semiconductor die such that at least portions of the first and second lands are exposed in and substantially flush with the bottom surface of the package body.

公开(公告)号：US20160172277A1

公开(公告)日：2016-06-16

申请号：US15043572

申请日：2016-02-14

Applicant: Amkor Technology, Inc.

Inventor： Kyoung Yeon Lee ,  Byong Jin Kim ,  Jae Min Bae ,  Hyung Il Jeon ,  Gi Jeong Kim ,  Ji Young Chung

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/50

CPC classification number: H01L23/49548 ,  H01L21/4828 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2021/60007 ,  H01L2224/13101 ,  H01L2224/16245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: In one embodiment, a method for forming a package substrate includes selectively removing portions of a lead frame to form cavities and filling the cavities with a resin layer to define an adhesion pad and a land structure. Top portions of the lead frame are selectively removed to isolate the adhesion pad and the land structure from each other, to expose a top surface of the resin layer, and to form at least one land having a part with a relatively greater size than the size of a respective lower part.

Abstract translation: 在一个实施例中，用于形成封装衬底的方法包括选择性地去除引线框架的部分以形成空腔并用树脂层填充空腔以限定粘合垫和焊盘结构。 引线框架的顶部部分被选择性地移除以将粘合垫和焊盘结构彼此隔离，以暴露树脂层的顶表面，并且形成至少一个具有比尺寸相对更大的部分的焊盘 的相应下部。

公开(公告)号：US09293398B2

公开(公告)日：2016-03-22

申请号：US14072845

申请日：2013-11-06

Applicant: Amkor Technology, Inc.

Inventor： Kyoung Yeon Lee ,  Byong Jin Kim ,  Jae Min Bae ,  Hyung Il Jeon ,  Gi Jeong Kim ,  Ji Young Chung

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L21/4828 ,  H01L23/3121 ,  H01L23/49548 ,  H01L23/49861 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/92247 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In one embodiment, a method for forming a package substrate includes selectively removing portions of a lead frame to form cavities and filling the cavities with a resin layer to define an adhesion pad and a land structure. Top portions of the lead frame are selectively removed to isolate the adhesion pad and the land structure from each other, to expose a top surface of the resin layer, and to form at least one land having a part with a relatively greater size than the size of a respective lower part.

Abstract translation: 在一个实施例中，用于形成封装衬底的方法包括选择性地去除引线框架的部分以形成空腔并用树脂层填充空腔以限定粘合垫和焊盘结构。 引线框架的顶部部分被选择性地移除以将粘合垫和焊盘结构彼此隔离，以暴露树脂层的顶表面，并且形成至少一个具有比尺寸相对更大的部分的焊盘 的相应下部。

公开(公告)号：US20150115422A1

公开(公告)日：2015-04-30

申请号：US14521417

申请日：2014-10-22

Applicant: Amkor Technology, Inc.

Inventor： Hyung Il Jeon ,  Ji Young Chung ,  Byong Jin Kim ,  In Bae Park ,  Jae Min Bae ,  No Sun Park

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49503 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49572 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13138 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16245 ,  H01L2224/16258 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/00014

Abstract: In one embodiment, an electronic package structure includes a lead having a first width. An electronic chip having a conductive bump on a major surface, the conductive bump has a second width greater than the first width. The conductive bump is attached to the lead such that a portion of the conductive bump extends to at least partially surround a side surface of the lead. A molding compound resin encapsulates the electronic chip, the conductive bump, and at least a portion of the lead. The lead is configured so strengthen the joining force between the lead and conductive bump.

Abstract translation: 在一个实施例中，电子封装结构包括具有第一宽度的引线。 一种在主表面上具有导电凸块的电子芯片，所述导电凸块具有大于所述第一宽度的第二宽度。 导电凸块附接到引线，使得导电凸块的一部分延伸到至少部分地围绕引线的侧表面。 模塑复合树脂封装电子芯片，导电凸块和引线的至少一部分。 引线被配置为加强引线和导电凸块之间的接合力。

公开(公告)号：US20140131848A1

公开(公告)日：2014-05-15

申请号：US14072845

申请日：2013-11-06

Applicant: Amkor Technology, Inc.

Inventor： Kyoung Yeon Lee ,  Byong Jin Kim ,  Jae Min Bae ,  Hyung Il Jeon ,  Gi Jeong Kim ,  Ji Young Chung

IPC: H01L21/48 ,  H01L23/495

CPC classification number: H01L23/49575 ,  H01L21/4828 ,  H01L23/3121 ,  H01L23/49548 ,  H01L23/49861 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/92247 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In one embodiment, a method for forming a package substrate includes selectively removing portions of a lead frame to form cavities and filling the cavities with a resin layer to define an adhesion pad and a land structure. Top portions of the lead frame are selectively removed to isolate the adhesion pad and the land structure from each other, to expose a top surface of the resin layer, and to form at least one land having a part with a relatively greater size than the size of a respective lower part.

Abstract translation: 在一个实施例中，用于形成封装衬底的方法包括选择性地去除引线框架的部分以形成空腔并用树脂层填充空腔以限定粘合垫和焊盘结构。 引线框架的顶部部分被选择性地移除以将粘合垫和焊盘结构彼此隔离，以暴露树脂层的顶表面，并且形成至少一个具有比尺寸相对更大的部分的焊盘 的相应下部。

公开(公告)号：US09966652B2

公开(公告)日：2018-05-08

申请号：US14931750

申请日：2015-11-03

Applicant: Amkor Technology, Inc.

Inventor： Marc Alan Mangrum ,  Hyung Jun Cho ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Min Bae ,  Seung Mo Kim ,  Young Ju Lee

IPC: H01Q1/50 ,  H01Q1/22 ,  H01Q9/04

CPC classification number: H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19107 ,  H01Q9/0407 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A packaged electronic device includes an integrated antenna as part of a conductive leadframe. The conductive leadframe includes a die paddle have an elongated conductive beam structure configured as a transmission line, and a ground plane structure disposed surrounding the die paddle. The ground plane includes a gap where the transmission line extends to an edge of the packaged electronic device. In one embodiment, selected leads within the leadframe are configured with conductive connective structures as ground pins, source pins, and/or wave guides. In an alternate embodiment, a portion of the integrated antenna is embedded and partially exposed within the body of the packaged electronic device.

公开(公告)号：US20170125881A1

公开(公告)日：2017-05-04

申请号：US14931750

申请日：2015-11-03

Applicant: Amkor Technology, Inc.

Inventor： Marc Alan Mangrum ,  Hyung Jun Cho ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Min Bae ,  Seung Mo Kim ,  Young Ju Lee

IPC: H01Q1/22 ,  H01Q9/04

CPC classification number: H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19107 ,  H01Q9/0407 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A packaged electronic device includes an integrated antenna as part of a conductive leadframe. The conductive leadframe includes a die paddle have an elongated conductive beam structure configured as a transmission line, and a ground plane structure disposed surrounding the die paddle. The ground plane includes a gap where the transmission line extends to an edge of the packaged electronic device. In one embodiment, selected leads within the leadframe are configured with conductive connective structures as ground pins, source pins, and/or wave guides. In an alternate embodiment, a portion of the integrated antenna is embedded and partially exposed within the body of the packaged electronic device.

公开(公告)号：US09543235B2

公开(公告)日：2017-01-10

申请号：US14875672

申请日：2015-10-05

Applicant: Amkor Technology, Inc.

Inventor： Hyung Il Jeon ,  Ji Young Chung ,  Byong Jin Kim ,  In Bae Park ,  Jae Min Bae ,  No Sun Park

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49572 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13138 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16245 ,  H01L2224/16258 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/00014

Abstract: In one embodiment, an electronic package structure includes a lead having a first width. An electronic chip having a conductive bump on a major surface, the conductive bump has a second width greater than the first width. The conductive bump is attached to the lead such that a portion of the conductive bump extends to at least partially surround a side surface of the lead. A molding compound resin encapsulates the electronic chip, the conductive bump, and at least a portion of the lead. The lead is configured so strengthen the joining force between the lead and conductive bump.

Abstract translation: 在一个实施例中，电子封装结构包括具有第一宽度的引线。 一种在主表面上具有导电凸块的电子芯片，所述导电凸块具有大于所述第一宽度的第二宽度。 导电凸块附接到引线，使得导电凸块的一部分延伸到至少部分地围绕引线的侧表面。 模塑复合树脂封装电子芯片，导电凸块和引线的至少一部分。 引线被配置为加强引线和导电凸块之间的接合力。

公开(公告)号：US20190057919A1

公开(公告)日：2019-02-21

申请号：US16114589

申请日：2018-08-28

Applicant: Amkor Technology, Inc.

Inventor： Jin Young Khim ,  Ji Young Chung ,  Ju Hoon Yoon ,  Kwang Woong Ahn ,  Ho Jeong Lim ,  Tae Yong Lee ,  Jae Min Bae

IPC: H01L23/31 ,  H01L21/683 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.

公开(公告)号：US09431334B2

公开(公告)日：2016-08-30

申请号：US14593310

申请日：2015-01-09

Applicant: Amkor Technology, Inc.

Inventor： Hyung Il Jeon ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Min Bae ,  Tae Ki Kim

IPC: H01L23/28 ,  H01L23/498 ,  H01L21/78 ,  H01L21/48 ,  H01L23/31 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15321 ,  H01L2924/1533 ,  H01L2924/18161 ,  H01L2224/81

Abstract: In one embodiment, a semiconductor device includes a single layer substrate having an insulation layer and conductive patterns on a first surface of the insulation layer. A semiconductor die is attached on a first surface of the single layer substrate and electrically connected to the conductive patterns. Conductive bumps are also on the first surface of the single layer substrate and electrically connected to the semiconductor die through the conductive patterns. An encapsulant overlaps at least portions of the first surface of the single layer substrate. The conductive bumps are at least partially exposed in the encapsulant.

Abstract translation: 在一个实施例中，半导体器件包括在绝缘层的第一表面上具有绝缘层和导电图案的单层衬底。 半导体管芯安装在单层衬底的第一表面上并电连接到导电图案。 导电凸块也在单层基板的第一表面上并且通过导电图案电连接到半导体管芯。 密封剂与单层基材的第一表面的至少部分重叠。 导电凸块至少部分地暴露在密封剂中。