公开(公告)号：US10032705B2

公开(公告)日：2018-07-24

申请号：US15149141

申请日：2016-05-08

Applicant: Amkor Technology, Inc.

Inventor： Jae Ung Lee ,  Yung Woo Lee ,  EunNaRa Cho ,  Dong Hyun Bang ,  Wook Choi ,  KooWoong Jeong ,  Byong Jin Kim ,  Min Chul Shin ,  Ho Jeong Lim ,  Ji Hyun Kim ,  Chang Hun Kim

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.

公开(公告)号：US09966652B2

公开(公告)日：2018-05-08

申请号：US14931750

申请日：2015-11-03

Applicant: Amkor Technology, Inc.

Inventor： Marc Alan Mangrum ,  Hyung Jun Cho ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Min Bae ,  Seung Mo Kim ,  Young Ju Lee

IPC: H01Q1/50 ,  H01Q1/22 ,  H01Q9/04

CPC classification number: H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19107 ,  H01Q9/0407 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A packaged electronic device includes an integrated antenna as part of a conductive leadframe. The conductive leadframe includes a die paddle have an elongated conductive beam structure configured as a transmission line, and a ground plane structure disposed surrounding the die paddle. The ground plane includes a gap where the transmission line extends to an edge of the packaged electronic device. In one embodiment, selected leads within the leadframe are configured with conductive connective structures as ground pins, source pins, and/or wave guides. In an alternate embodiment, a portion of the integrated antenna is embedded and partially exposed within the body of the packaged electronic device.

公开(公告)号：US09922919B2

公开(公告)日：2018-03-20

申请号：US14984064

申请日：2015-12-30

Applicant: Amkor Technology, Inc.

Inventor： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Ji Young Chung

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49827 ,  H01L21/4828 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49861 ,  H01L2224/16225 ,  H01L2924/181 ,  H01L2924/00012

Abstract: In one embodiment, an electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns and a package body encapsulating the top surface of the insulating material and the electronic device, wherein the bottom land surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer.

公开(公告)号：US20170125881A1

公开(公告)日：2017-05-04

申请号：US14931750

申请日：2015-11-03

Applicant: Amkor Technology, Inc.

Inventor： Marc Alan Mangrum ,  Hyung Jun Cho ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Min Bae ,  Seung Mo Kim ,  Young Ju Lee

IPC: H01Q1/22 ,  H01Q9/04

CPC classification number: H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19107 ,  H01Q9/0407 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A packaged electronic device includes an integrated antenna as part of a conductive leadframe. The conductive leadframe includes a die paddle have an elongated conductive beam structure configured as a transmission line, and a ground plane structure disposed surrounding the die paddle. The ground plane includes a gap where the transmission line extends to an edge of the packaged electronic device. In one embodiment, selected leads within the leadframe are configured with conductive connective structures as ground pins, source pins, and/or wave guides. In an alternate embodiment, a portion of the integrated antenna is embedded and partially exposed within the body of the packaged electronic device.

公开(公告)号：US09613829B1

公开(公告)日：2017-04-04

申请号：US15148895

申请日：2016-05-06

Applicant: Amkor Technology, Inc.

Inventor： Seung Woo Lee ,  Byong Jin Kim ,  Won Bae Bang ,  Sang Goo Kang

IPC: H01L29/84 ,  H01L21/48 ,  H01L23/31 ,  H01L23/495 ,  H01L23/522 ,  H01L21/56

CPC classification number: H01L23/49861 ,  H01L21/4839 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process. In one embodiment, the method for fabricating a semiconductor package includes forming a frame on a carrier, forming a first pattern layer on the frame, first encapsulating the frame and the first pattern layer using a first encapsulant, forming conductive vias electrically connected to the first pattern layer while passing through the first encapsulant, forming a second pattern layer electrically connected to the conductive vias on the first encapsulant, forming a first solder mask formed on the first encapsulant and exposing a portion of the second pattern layer to the outside, removing the frame by an etching process and etching a portion of the first pattern layer, and attaching a semiconductor die to the first pattern layer.

公开(公告)号：US09543235B2

公开(公告)日：2017-01-10

申请号：US14875672

申请日：2015-10-05

Applicant: Amkor Technology, Inc.

Inventor： Hyung Il Jeon ,  Ji Young Chung ,  Byong Jin Kim ,  In Bae Park ,  Jae Min Bae ,  No Sun Park

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49572 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13138 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16245 ,  H01L2224/16258 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/00014

Abstract: In one embodiment, an electronic package structure includes a lead having a first width. An electronic chip having a conductive bump on a major surface, the conductive bump has a second width greater than the first width. The conductive bump is attached to the lead such that a portion of the conductive bump extends to at least partially surround a side surface of the lead. A molding compound resin encapsulates the electronic chip, the conductive bump, and at least a portion of the lead. The lead is configured so strengthen the joining force between the lead and conductive bump.

Abstract translation: 在一个实施例中，电子封装结构包括具有第一宽度的引线。 一种在主表面上具有导电凸块的电子芯片，所述导电凸块具有大于所述第一宽度的第二宽度。 导电凸块附接到引线，使得导电凸块的一部分延伸到至少部分地围绕引线的侧表面。 模塑复合树脂封装电子芯片，导电凸块和引线的至少一部分。 引线被配置为加强引线和导电凸块之间的接合力。

公开(公告)号：US09513254B2

公开(公告)日：2016-12-06

申请号：US14455975

申请日：2014-08-11

Applicant: Amkor Technology, Inc.

Inventor： Hyung II Jeon ,  Ji Young Chung ,  Chan Ha Hwang ,  Byong Jin Kim ,  Yung Woo Lee ,  Do Hyun Na ,  Jae Ung Lee

IPC: B01L3/00 ,  G01N33/487 ,  H01L23/433 ,  G01N27/447 ,  H01L23/34

CPC classification number: G01N27/44791 ,  B01L3/502707 ,  B01L3/502715 ,  B01L3/50273 ,  B01L3/502761 ,  B01L2200/12 ,  B01L2300/0645 ,  B01L2300/0816 ,  B01L2300/0858 ,  B01L2400/0406 ,  B01L2400/0415 ,  G01N33/48707 ,  G01N33/48721 ,  H01L23/4334 ,  H01L2924/0002 ,  Y10T29/4913 ,  H01L2924/00

Abstract: In one embodiment, a microfluidic sensor device includes microfluidic sensor mounted on and electrically connected a micro lead frame substrate. The microfluidic sensor is molded to form a package body. The package body includes a molded panel portion and, in some embodiments, a mask portion having one or more open channels, sealed channels, and/or a sealed chamber exposing an active surface of the microfluidic sensor. The molded panel portions and mask portions are configured to allow a material to dynamically or statically contact the microfluidic sensor for analysis.

Abstract translation: 在一个实施例中，微流体传感器装置包括安装在微引线框架基板上并电连接微引线框架基板的微流体传感器。 微流体传感器被模制以形成包装体。 封装主体包括模制板部分，并且在一些实施例中，具有一个或多个开放通道，密封通道的掩模部分和/或暴露微流体传感器的有效表面的密封室。 模制板部分和掩模部分被配置成允许材料动态地或静态地接触微流体传感器用于分析。

公开(公告)号：US20160276178A1

公开(公告)日：2016-09-22

申请号：US15073219

申请日：2016-03-17

Applicant: Amkor Technology, Inc.

Inventor： Yi Seul Han ,  Jae Beum Shim ,  Byong Jin Kim ,  In Bae Park

IPC: H01L21/56 ,  H01L21/683 ,  H01L21/288 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L21/6836 ,  H01L21/2885 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11009 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/1329 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13566 ,  H01L2224/136 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/0231

Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices made thereby, that utilize a film assist mold process.

Abstract translation: 电子设备和制造电子设备的方法。 作为非限制性示例，本公开的各个方面提供制造电子设备和由此制造的电子设备的各种方法，其利用膜辅助模制过程。

公开(公告)号：US20140327122A1

公开(公告)日：2014-11-06

申请号：US14268877

申请日：2014-05-02

Applicant: Amkor Technology, Inc.

Inventor： Hyeong Il Jeon ,  Hyung Kook Chung ,  Hong Bae Kim ,  Byong Jin Kim

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49541 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/00

Abstract: In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes.

Abstract translation: 在一个实施例中，微引线框架结构包括形成在引线和/或连接结构上的一个或多个刚度增强结构。 刚性加强结构可以通过将微引线框架的预定部分留在包括例如内引线的一部分，外引线的一部分以及连接条的部分，其组合和其它结构的全厚度而形成。 刚度增强结构被配置为减少由组装过程引起的变形缺陷和电短缺。

公开(公告)号：US20130264694A1

公开(公告)日：2013-10-10

申请号：US13750532

申请日：2013-01-25

Applicant: AMKOR TECHNOLOGY, INC.

Inventor： Sung Gyu Kim ,  Byong Jin Kim ,  Gi Jeong Kim

IPC: H01L21/56 ,  H01L23/495

CPC classification number: H01L21/56 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49558 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00014

Abstract: In one embodiment, a semiconductor device includes a leadframe structure. A semiconductor die is attached to a die pad. Land connect bars are spaced apart from the die pad and a plurality of lands are between the land connect bars and the die pad and are spaced apart therefrom. Insulation members are adhered to the land connect bars and the plurality of lands to hold the land connect bars and the plurality of lands together and to electrically isolate them. An encapsulant covers the semiconductor die and at least portions of the plurality of lands, the die pad, and the land connect bars and further fills spaces between the land connect bars and the plurality of lands.

Abstract translation: 在一个实施例中，半导体器件包括引线框架结构。 将半导体管芯附接到管芯焊盘。 接地连接杆与管芯焊盘间隔开，并且多个焊盘位于焊盘连接杆和焊盘之间并且与焊盘间隔开。 绝缘构件粘附到陆地连接杆和多个土地上以将土地连接杆和多个土地区保持在一起并将它们电隔离。 密封剂覆盖半导体管芯和多个焊盘的至少部分，管芯焊盘和焊盘连接条，并进一步填充焊盘连接条和多个焊盘之间的空间。