Adaptive spectral enhancement and harmonic separation
    3.
    发明授权
    Adaptive spectral enhancement and harmonic separation 有权
    自适应光谱增强和谐波分离

    公开(公告)号:US08964890B2

    公开(公告)日:2015-02-24

    申请号:US13910779

    申请日:2013-06-05

    CPC classification number: H03H21/0021 H03H21/0012

    Abstract: A circuit and method perform adaptive spectral enhancement at a frequency ω1 (also called “fundamental” frequency) on an input signal y which includes electromagnetic interference (EMI) at an unknown frequency, to generate a fundamental-enhanced signal φ1 (or its complement). The fundamental-enhanced signal φ1 (or complement) is thereafter used in a notching circuit (also called “fundamental notching” circuit) to generate a fundamental-notched signal y-φ1. The fundamental-notched signal y-φ1is itself enhanced to generate a harmonic-enhanced signal φ2 that is used to notch the fundamental-notched signal y-φ1again, in one or more additional notching circuits that are connected in series with the fundamental notching circuit. The result (“cascaded-harmonic-notched” signal) is relatively free of EMI noise (fundamental and harmonics), and is used as an error signal for an adaptation circuit that in turn identifies the fundamental frequency ω1. Use of a cascaded-harmonic-notched signal as the error signal improves speed of convergence of adaptation.

    Abstract translation: 电路和方法在包括未知频率的电磁干扰(EMI)的输入信号y上对频率ω1(也称为“基本”频率)执行自适应频谱增强,以产生基本增强信号&phgr; 1(或其 补充)。 1,然后在切口电路(也称为“基本陷波”电路)中使用基本增强的信号& 1(或补码)以产生基本缺口信号y-&phgr; 1。 基本缺陷信号y-&phgr; 1本身被增强以产生用于在串联连接的一个或多个附加凹口电路中陷入基本缺陷信号y-&phgr; 1again的谐波增强信号&ph2; 与基本的开槽电路。 结果(“级联谐波陷波”信号)相对没有EMI噪声(基波和谐波),并被用作自适应电路的误差信号,自适应电路进而识别基频ω1。 使用级联谐波陷波信号作为误差信号提高适应性收敛速度。

    Product coded modulation scheme based on leech lattice and binary and nonbinary codes
    4.
    发明授权
    Product coded modulation scheme based on leech lattice and binary and nonbinary codes 有权
    基于水蛭晶格和二进制和非二进制代码的商品编码调制方案

    公开(公告)号:US09467177B1

    公开(公告)日:2016-10-11

    申请号:US14466355

    申请日:2014-08-22

    Inventor: Dariush Dabiri

    Abstract: A transceiver architecture contains an encoder and a decoder for communicating high speed transmissions. The encoder modulates signal data based on an FEC code that has a symbol size that is not matched to a symbol size of a hexacode. Any code where the symbol size is less than the sample size for coding can be serially concatenated. During decoding the multilevel decoding leech lattice and FEC decoder iteratively passes their outputs back and forth to each other until the encoded bits are decoded.

    Abstract translation: 收发机架构包含用于传送高速传输的编码器和解码器。 编码器基于具有与六进制码的符号大小不匹配的符号大小的FEC码来对信号数据进行调制。 符号大小小于编码的样本大小的任何代码都可以串行连接。 在解码期间,多级解码水蛭格和FEC解码器将它们的输出相互反复地传递给彼此直到编码比特被解码。

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