公开(公告)号：US20230223255A1

公开(公告)日：2023-07-13

申请号：US18153272

申请日：2023-01-11

Applicant: ASM IP Holding, B.V.

Inventor： Steven Van Aerde ,  Wilco Verweij ,  Bert Jongbloed ,  Dieter Pierreux ,  Kelly Houben ,  Rami Khazaka ,  Frederick Aryeetey ,  Peter Westrom ,  Omar Elleuch ,  Caleb Miskin

IPC: H01L21/02 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68

CPC classification number: H01L21/0257 ,  C30B25/165 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  H01L21/0262 ,  H01L21/02532

Abstract: A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing the plurality of substrates to a process chamber. A plurality of deposition cycles is executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial stack comprises a plurality of epitaxial pairs, wherein the epitaxial pairs each comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. Each deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer. The first deposition pulse or the second deposition pulse further comprises a provision of a dopant precursor gas to the process chamber.

公开(公告)号：US20240203734A1

公开(公告)日：2024-06-20

申请号：US18540329

申请日：2023-12-14

Applicant: ASM IP Holding B.V.

Inventor： Maritza Mujica ,  Ernesto Suarez ,  Amir Kajbafvala ,  Rami Khazaka ,  Arum Murali ,  Frederick Aryeetey ,  Yanfu Lu ,  Caleb Miskin ,  Alexandros Demos ,  Bibek Karki

IPC: H01L21/02 ,  C30B25/10 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  H01L29/78

CPC classification number: H01L21/0262 ,  C30B25/10 ,  C30B25/16 ,  C30B29/06 ,  C30B29/52 ,  C30B29/68 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/7848 ,  H01L29/167

Abstract: Methods for forming multilayer structures are disclosed. The methods may include, seating a substrate within a chamber body, and regulating a temperature profile across an upper surface of the substrate during each individual deposition phase of multiphase deposition process. Semiconductor device structures including multilayer structures are also disclosed.

公开(公告)号：US20230125884A1

公开(公告)日：2023-04-27

申请号：US18048145

申请日：2022-10-20

Applicant: ASM IP Holding, B.V.

Inventor： Gregory Deye ,  Arun Murali ,  Frederick Aryeetey ,  Caleb Miskin ,  Alexandros Demos

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/67 ,  H01L21/687

Abstract: A material layer deposition method includes supporting a substrate in a preclean module and exposing the substrate to a preclean etchant while supported within the preclean module. The substrate is transferred to a deposition module and exposed to an adsorbate while supported within the deposition module. A material layer is the deposited onto the substrate while supported within the deposition module subsequent to exposing the substrate to the adsorbate. Semiconductor processing systems and computer program products are also described.

公开(公告)号：US20250137723A1

公开(公告)日：2025-05-01

申请号：US18928413

申请日：2024-10-28

Applicant: ASM IP Holding B.V.

Inventor： Felix Rabinovich ,  Terry Parde ,  Gary Urban Keppers ,  Amin Azimi ,  Alicia Almeda ,  Fauhmee Oudeif ,  Amir Kajbafvala ,  Arun Murali ,  Frederick Aryeetey ,  Alexandros Demos ,  Nayna Khosla ,  Caleb Miskin ,  Hichem M'Saad ,  Shivaji Peddeti ,  Steven Reiter

IPC: F27B17/00 ,  B28B11/02 ,  B28D1/02 ,  B28D1/14 ,  B28D1/18

Abstract: A chamber body includes a ceramic weldment having a lower wall, a sidewall, and an upper wall. The sidewall is coupled to the lower wall by a sidewall-to-lower wall weld and the upper wall is coupled to the sidewall by a sidewall-to-upper wall weld. The upper wall has an upper wall plate portion and an upper wall rib portion extending therefrom formed from a singular quartz workpiece using a subtractive manufacturing technique, the upper wall further having a unwelded ribbed region overlying the lower wall. Chamber arrangements, semiconductor processing systems and related methods of making chamber bodies and depositing material layers onto substrates supported within chamber bodies are also described.

公开(公告)号：US20250112064A1

公开(公告)日：2025-04-03

申请号：US18900352

申请日：2024-09-27

Applicant: ASM IP Holding B.V.

Inventor： Amir Kajbafvala ,  Arun Murali ,  Caleb Miskin ,  Frederick Aryeetey ,  Alexandros Demos

IPC: H01L21/67

Abstract: A chamber arrangement for a semiconductor processing system includes a chamber body, a substrate support, a first chamber pyrometer, and a second chamber pyrometer. The chamber body has an exterior surface, a hollow interior, and the substrate support is supported for rotation within the interior of the chamber body. The first chamber pyrometer and second chamber pyrometer are optically coupled to the exterior surface of the chamber body. The first chamber pyrometer is configured to acquire a first temperature measurement at a first location on the exterior surface of the chamber body, and the second chamber pyrometer is configured to acquire a second temperature measurement at a second location on the exterior surface of the chamber body. The second location is offset from the first location to throttle temperature across the exterior surface of the chamber body between the first location and the second location. Material layer deposition methods and computer program products are also described.

公开(公告)号：US20240175138A1

公开(公告)日：2024-05-30

申请号：US18518393

申请日：2023-11-22

Applicant: ASM IP HOlding B.V.

Inventor： Fan Gao ,  Peipei Gao ,  Xing Lin ,  Arun Murali ,  Gregory Deye ,  Frederick Aryeetey ,  Amir Kajbafvala ,  Caleb Miskin ,  Alexandros Demos

IPC: C23C16/52 ,  C23C16/44 ,  C23C16/46 ,  H01L21/67

CPC classification number: C23C16/52 ,  C23C16/4412 ,  C23C16/46 ,  H01L21/67017 ,  H01L21/67126 ,  H01L21/67253

Abstract: Systems and methods controlling the pressure differential between two sealed chambers connected by a gate valve in preparation for a gate valve opening event. Such systems and methods may adjust gas pressure in at least one of the chambers, if needed, until the pressure differential between the two chambers is at a predetermined pressure differential level. In some more specific examples, one chamber may constitute a substrate handling chamber, the other chamber may constitute a reaction chamber (e.g., for depositing one or more layers on a surface of a substrate), and the gate valve opening event may allow a substrate to be transferred from one chamber to the other (e.g., from the reaction chamber into the substrate handling chamber).