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    SYSTEMS AND METHODS FOR ATOMIC LAYER DEPOSITION
    3.
    发明申请
    SYSTEMS AND METHODS FOR ATOMIC LAYER DEPOSITION 审中-公开

    公开(公告)号：US20190112707A1

    公开(公告)日：2019-04-18

    申请号：US15785231

    申请日：2017-10-16

    Applicant: ASM IP HOLDING B.V.

    Inventor： Eric Jen Cheng Liu

    IPC: C23C16/455 ,  C23C16/52 ,  C23C16/44

    Abstract: An atomic layer deposition (ALD) method can include pulsing a first reactant vapor into a reactor assembly. The first reactant vapor is supplied to a first reactant gas line. An inactive gas is supplied to a first inactive gas line at a first flow rate. The first reactant vapor and the inactive gas are fed to the reactor assembly by way of a first feed line. The reactor assembly is purged by supplying the inactive gas to the first inactive gas line at a second flow rate higher than the first flow rate. A first portion of the inactive gas can be fed back along a diffusion barrier portion of the first reactant gas line to provide an inert gas valve (IGV) upstream of the first inactive gas line. A second portion of the inactive gas can be fed to the reactor assembly by way of the first feed line.

    FORMATION OF GATE STACKS COMPRISING A THRESHOLD VOLTAGE TUNING LAYER
    5.
    发明公开
    FORMATION OF GATE STACKS COMPRISING A THRESHOLD VOLTAGE TUNING LAYER 审中-公开

    公开(公告)号：US20230197796A1

    公开(公告)日：2023-06-22

    申请号：US17660389

    申请日：2022-04-22

    Applicant: ASM IP HOLDING B.V.

    Inventor： Fu Tang ,  Eric James Shero ,  Gejian Zhao ,  Eric Jen Cheng Liu

    IPC: H01L29/40 ,  H01L21/28

    CPC classification number: H01L29/401 ,  H01L21/28088

    Abstract: Threshold voltage (Vt) tuning layers may be sensitive to etching by reactants used to deposit overlying gate material, such as metal nitride. Methods for depositing Vt tuning layers are provided. In some embodiments Vt tuning layers may comprise a Vt tuning material in a neutral matrix. In some embodiments, processes for reducing or eliminating the etching of Vt tuning layers by halide reactants are described. In some embodiments a Vt tuning layer, such as a metal oxide layer, is treated by a nitridation process following deposition and prior to subsequent deposition of a metal nitride capping layer. In some embodiments an etch-protective layer, such as a NbO layer, is deposited over a Vt tuning layer prior to deposition of an overlying metal nitride layer.

    METHOD AND SYSTEM TO REDUCE OUTGASSING IN A REACTION CHAMBER
    6.
    发明申请
    METHOD AND SYSTEM TO REDUCE OUTGASSING IN A REACTION CHAMBER 有权
    减少反应室中出现的方法和系统

    公开(公告)号：US20150140210A1

    公开(公告)日：2015-05-21

    申请号：US14606364

    申请日：2015-01-27

    Applicant: ASM IP HOLDING B.V.

    Inventor： Sung-Hoon Jung ,  Petri Raisanen ,  Eric Jen Cheng Liu ,  Mike Schmotzer

    IPC: C23C16/44 ,  C23C16/455

    CPC classification number: C23C16/4404 ,  C23C16/4405 ,  C23C16/45525 ,  C23C16/45534 ,  C23C16/45544

    Abstract: Systems and methods of reducing outgassing of a substance within a reaction chamber of a reactor are disclosed. Exemplary methods include depositing a barrier layer within the reaction chamber and using a scavenging precursor to react with species on a surface of the reaction chamber. Exemplary systems include gas-phase deposition systems, such as atomic layer deposition systems, which include a barrier layer source and/or a scavenging precursor source fluidly coupled to a reaction chamber of the system.

    Abstract translation: 公开了在反应器的反应室内减少物质的除气的系统和方法。 示例性方法包括在反应室内沉积阻挡层并使用清除前体与反应室表面上的物质反应。 示例性系统包括气相沉积系统，例如原子层沉积系统，其包括流体耦合到系统的反应室的阻挡层源和/或清除前体源。

    SYSTEMS AND METHODS FOR ATOMIC LAYER DEPOSITION
    7.
    发明申请
    SYSTEMS AND METHODS FOR ATOMIC LAYER DEPOSITION 有权

    公开(公告)号：US20210156026A1

    公开(公告)日：2021-05-27

    申请号：US17162929

    申请日：2021-01-29

    Applicant: ASM IP HOLDING B.V.

    Inventor： Eric Jen Cheng Liu

    IPC: C23C16/455 ,  C23C16/44 ,  C23C16/52 ,  H01J37/32

    Abstract: An atomic layer deposition (ALD) method can include pulsing a first reactant vapor into a reactor assembly. The first reactant vapor is supplied to a first reactant gas line. An inactive gas is supplied to a first inactive gas line at a first flow rate. The first reactant vapor and the inactive gas are fed to the reactor assembly by way of a first feed line. The reactor assembly is purged by supplying the inactive gas to the first inactive gas line at a second flow rate higher than the first flow rate. A first portion of the inactive gas can be fed back along a diffusion barrier portion of the first reactant gas line to provide an inert gas valve (IGV) upstream of the first inactive gas line. A second portion of the inactive gas can be fed to the reactor assembly by way of the first feed line.

    Systems and methods for atomic layer deposition
    8.
    发明授权
    Systems and methods for atomic layer deposition 有权

    公开(公告)号：US10927459B2

    公开(公告)日：2021-02-23

    申请号：US15785231

    申请日：2017-10-16

    Applicant: ASM IP HOLDING B.V.

    Inventor： Eric Jen Cheng Liu

    IPC: C23C16/455 ,  C23C16/44 ,  C23C16/52 ,  H01J37/32 ,  C30B25/14 ,  C30B23/02 ,  H01L21/02

    Abstract: An atomic layer deposition (ALD) method can include pulsing a first reactant vapor into a reactor assembly. The first reactant vapor is supplied to a first reactant gas line. An inactive gas is supplied to a first inactive gas line at a first flow rate. The first reactant vapor and the inactive gas are fed to the reactor assembly by way of a first feed line. The reactor assembly is purged by supplying the inactive gas to the first inactive gas line at a second flow rate higher than the first flow rate. A first portion of the inactive gas can be fed back along a diffusion barrier portion of the first reactant gas line to provide an inert gas valve (IGV) upstream of the first inactive gas line. A second portion of the inactive gas can be fed to the reactor assembly by way of the first feed line.

    Formation of gate stacks comprising a threshold voltage tuning layer
    10.
    发明授权
    Formation of gate stacks comprising a threshold voltage tuning layer 有权

    公开(公告)号：US12295163B2

    公开(公告)日：2025-05-06

    申请号：US17660389

    申请日：2022-04-22

    Applicant: ASM IP HOLDING B.V.

    Inventor： Fu Tang ,  Eric James Shero ,  Gejian Zhao ,  Eric Jen Cheng Liu

    IPC: H10D64/01 ,  H01L21/28

    Abstract: Threshold voltage (Vt) tuning layers may be sensitive to etching by reactants used to deposit overlying gate material, such as metal nitride. Methods for depositing Vt tuning layers are provided. In some embodiments Vt tuning layers may comprise a Vt tuning material in a neutral matrix. In some embodiments, processes for reducing or eliminating the etching of Vt tuning layers by halide reactants are described. In some embodiments a Vt tuning layer, such as a metal oxide layer, is treated by a nitridation process following deposition and prior to subsequent deposition of a metal nitride capping layer. In some embodiments an etch-protective layer, such as a NbO layer, is deposited over a Vt tuning layer prior to deposition of an overlying metal nitride layer.

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