公开(公告)号：US20170235700A1

公开(公告)日：2017-08-17

申请号：US15374739

申请日：2016-12-09

Applicant: ATI TECHNOLOGIES ULC

Inventor： Shahin Solki ,  Stephen Morein ,  Mark S. Grossman

IPC: G06F13/42 ,  G06T1/60 ,  G06T1/20

CPC classification number: G06F13/4282 ,  G06F3/14 ,  G06F2213/0026 ,  G06T1/20 ,  G06T1/60 ,  G09G5/006 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/06

Abstract: Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors in one peripheral component can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

公开(公告)号：US11710209B2

公开(公告)日：2023-07-25

申请号：US17661824

申请日：2022-05-03

Applicant: ATI Technologies ULC

Inventor： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

IPC: G06T1/00 ,  G06T1/20 ,  G06F9/38 ,  G06T15/00 ,  G06T15/04 ,  G06T1/60 ,  G09G5/00 ,  G09G5/36

CPC classification number: G06T1/20 ,  G06F9/3851 ,  G06T1/60 ,  G06T15/005 ,  G06T15/04 ,  G09G5/001 ,  G09G5/363

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

公开(公告)号：US10957007B2

公开(公告)日：2021-03-23

申请号：US16424145

申请日：2019-05-28

Applicant: ATI Technologies ULC

Inventor： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

IPC: G06T1/00 ,  G06T1/20 ,  G06F9/38 ,  G06T15/00 ,  G06T15/04 ,  G06T1/60 ,  G09G5/00 ,  G09G5/36

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

公开(公告)号：US10467178B2

公开(公告)日：2019-11-05

申请号：US15374739

申请日：2016-12-09

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Shahin Solki ,  Stephen Morein ,  Mark S. Grossman

IPC: G06F13/42 ,  G06F3/14 ,  G09G5/36 ,  G06T1/20 ,  G06T1/60 ,  G09G5/00

Abstract: Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors in one peripheral component can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

公开(公告)号：US20160140687A1

公开(公告)日：2016-05-19

申请号：US15006802

申请日：2016-01-26

Applicant: ATI Technologies ULC

Inventor： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

IPC: G06T1/20 ,  G09G5/00 ,  G06T1/60 ,  G09G5/36

CPC classification number: G06T1/20 ,  G06F9/3851 ,  G06T1/60 ,  G06T15/005 ,  G06T15/04 ,  G09G5/001 ,  G09G5/363

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

公开(公告)号：US20140292784A1

公开(公告)日：2014-10-02

申请号：US14299600

申请日：2014-06-09

Applicant: ATI Technologies ULC

Inventor： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F9/3851 ,  G06T1/60 ,  G06T15/005 ,  G06T15/04 ,  G09G5/001 ,  G09G5/363

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract translation: 图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。 提供耦合到所述至少一个存储器件的仲裁器，其从所述多个像素命令线程中选择像素命令线程，以及从所述多个顶点命令线程中选择顶点命令线程。 仲裁器还从先前选择的像素命令线程和顶点命令线程中选择命令线程，该命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。

公开(公告)号：US20130215128A1

公开(公告)日：2013-08-22

申请号：US13846210

申请日：2013-03-18

Applicant: ATI Technologies ULC

Inventor： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F9/3851 ,  G06T1/60 ,  G06T15/005 ,  G06T15/04 ,  G09G5/001 ,  G09G5/363

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract translation: 图形处理系统包括存储多个像素命令线程和多个顶点命令线程的至少一个存储器件。 提供耦合到所述至少一个存储器件的仲裁器，其从所述多个像素命令线程中选择像素命令线程，以及从所述多个顶点命令线程中选择顶点命令线程。 仲裁器还从先前选择的像素命令线程和顶点命令线程中选择命令线程，该命令线程被提供给能够处理像素命令线程和顶点命令线程的命令处理引擎。

公开(公告)号：US20190279333A1

公开(公告)日：2019-09-12

申请号：US16424145

申请日：2019-05-28

Applicant: ATI Technologies ULC

Inventor： Laurent LEFEBVRE ,  Andrew Gruber ,  Stephen Morein

IPC: G06T1/20 ,  G09G5/36 ,  G09G5/00 ,  G06F9/38 ,  G06T15/04 ,  G06T15/00 ,  G06T1/60

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

公开(公告)号：US10346945B2

公开(公告)日：2019-07-09

申请号：US15901603

申请日：2018-02-21

Applicant: ATI Technologies ULC

Inventor： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

IPC: G06T1/00 ,  G06T1/20 ,  G06F9/38 ,  G06T15/00 ,  G06T15/04 ,  G06T1/60 ,  G09G5/00 ,  G09G5/36

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

公开(公告)号：US08775747B2

公开(公告)日：2014-07-08

申请号：US13847218

申请日：2013-03-19

Applicant: ATI Technologies ULC

Inventor： Joseph D. Macri ,  Stephen Morein ,  Ming-Ju E. Lee ,  Lin Chen

IPC: G06F13/00

CPC classification number: G06F12/00 ,  G06F13/4234 ,  G06F13/4243 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/1096

Abstract: A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

Abstract translation: 描述了用于执行字节写入的方法和系统，其中字节写入仅涉及仅写入多字节写入操作的特定字节。 实施例包括指示在字节写入操作中要写入哪些字节的掩码数据。 不使用专用的掩码引脚或专用掩码线。 在一个实施例中，掩码数据在数据线上传输，并响应于write_mask命令存储。 在一个实施例中，掩模数据作为写入命令的一部分被发送。