公开(公告)号：US20230186423A1

公开(公告)日：2023-06-15

申请号：US18106572

申请日：2023-02-07

Applicant: ATI Technologies ULC

Inventor： Stephen L. Morein ,  Laurent Lefebvre ,  Andrew E. Gruber ,  Andi Skende

IPC: G06T1/20 ,  G06T15/80 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T15/80 ,  G06T15/005

Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

公开(公告)号：US11379941B2

公开(公告)日：2022-07-05

申请号：US15415823

申请日：2017-01-25

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Todd Martin ,  Mangesh P. Nijasure ,  Randy W. Ramsey ,  Michael Mantor ,  Laurent Lefebvre

IPC: G06T1/20 ,  G06T15/00 ,  G06T15/40

Abstract: Improvements in the graphics processing pipeline are disclosed. More specifically, a new primitive shader stage performs tasks of the vertex shader stage or a domain shader stage if tessellation is enabled, a geometry shader if enabled, and a fixed function primitive assembler. The primitive shader stage is compiled by a driver from user-provided vertex or domain shader code, geometry shader code, and from code that performs functions of the primitive assembler. Moving tasks of the fixed function primitive assembler to a primitive shader that executes in programmable hardware provides many benefits, such as removal of a fixed function crossbar, removal of dedicated parameter and position buffers that are unusable in general compute mode, and other benefits.

公开(公告)号：US10169906B2

公开(公告)日：2019-01-01

申请号：US13853422

申请日：2013-03-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mark Fowler ,  Timothy Kelley ,  Mikko Alho ,  Mika Tuomi ,  Kiia Kallio ,  Patrick Klas Rudolf Buss ,  Jari Antero Komppa ,  Kaj Tuomi

IPC: G06T1/20 ,  G06T15/00

Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.

公开(公告)号：US20240135626A1

公开(公告)日：2024-04-25

申请号：US18402315

申请日：2024-01-02

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mark Fowler ,  Timothy Kelley ,  Mikko Alho ,  Mika Tuomi ,  Kiia Kallio ,  Patrick Klas Rudolf Buss ,  Jari Antero Komppa ,  Kaj Tuomi

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin intercepts computed until all of the respective bin intercepts are processed.

公开(公告)号：US11562459B2

公开(公告)日：2023-01-24

申请号：US17128388

申请日：2020-12-21

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Noor Mohammed Saleem Bijapur ,  Ashish Khandelwal ,  Laurent Lefebvre ,  Anirudh R. Acharya

IPC: G06F12/0804 ,  G06T1/60 ,  G06T1/20 ,  G06F12/0888 ,  G06F12/0806 ,  G09G5/39

Abstract: A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.

公开(公告)号：US10546365B2

公开(公告)日：2020-01-28

申请号：US15843968

申请日：2017-12-15

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mika Tuomi ,  Kiia Kallio

IPC: G06T3/40 ,  G06T1/20 ,  G06T3/00 ,  G06T15/80 ,  G06T15/00

Abstract: An apparatus, such as a head mounted device (HMD), includes one or more processors configured to implement a graphics pipeline that renders pixels in window space with a nonuniform pixel spacing. The apparatus also includes a first distortion function that maps the non-uniformly spaced pixels in window space to uniformly spaced pixels in raster space. The apparatus further includes a scan converter configured to sample the pixels in window space through the first distortion function. The scan converter is configured to render display pixels used to generate an image for display to a user based on the uniformly spaced pixels in raster space. In some cases, the pixels in the window space are rendered such that a pixel density per subtended area is constant across the user's field of view.

公开(公告)号：US20190122417A1

公开(公告)日：2019-04-25

申请号：US16179376

申请日：2018-11-02

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mark Fowler ,  Timothy Kelley ,  Mikko Alho ,  Mika Tuomi ,  Kiia Kallio ,  Patrick Klas Rudolf Buss ,  Jari Antero Komppa ,  Kaj Tuomi

IPC: G06T15/00

Abstract: A system, method and a non-transitory computer readable storage medium are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from one or more primitives. A bin is identified for processing the primitive batch. At least a portion of each primitive intersecting the identified bin is processed and a next bin for processing the primitive batch is identified based on an intercept walk order. The processing is iteratively repeated for the one or more primitives in the primitive batch for successive bins until all primitives of the primitive batch are completely processed. Then, the one or more primitives in the primitive batch are further processed.

公开(公告)号：US11880926B2

公开(公告)日：2024-01-23

申请号：US17745410

申请日：2022-05-16

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mark Fowler ,  Timothy Kelley ,  Mikko Alho ,  Mika Tuomi ,  Kiia Kallio ,  Patrick Klas Rudolf Buss ,  Jari Antero Komppa ,  Kaj Tuomi

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: A method, computer system, and a non-transitory computer-readable storage medium for performing primitive batch binning are disclosed. The method, computer system, and non-transitory computer-readable storage medium include techniques for generating a primitive batch from a plurality of primitives, computing respective bin intercepts for each of the plurality of primitives in the primitive batch, and shading the primitive batch by iteratively processing each of the respective bin intercepts computed until all of the respective bin intercepts are processed.

公开(公告)号：US11710209B2

公开(公告)日：2023-07-25

申请号：US17661824

申请日：2022-05-03

Applicant: ATI Technologies ULC

Inventor： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

IPC: G06T1/00 ,  G06T1/20 ,  G06F9/38 ,  G06T15/00 ,  G06T15/04 ,  G06T1/60 ,  G09G5/00 ,  G09G5/36

CPC classification number: G06T1/20 ,  G06F9/3851 ,  G06T1/60 ,  G06T15/005 ,  G06T15/04 ,  G09G5/001 ,  G09G5/363

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

公开(公告)号：US11551398B2

公开(公告)日：2023-01-10

申请号：US17008388

申请日：2020-08-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Mika Tuomi ,  Miikka Petteri Kangasluoma ,  Jan Henrik Achrenius ,  Laurent Lefebvre

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80 ,  G06T17/10 ,  G06T7/00 ,  G06T1/20

Abstract: Systems, apparatuses, and methods for implementing light volume rendering techniques are disclosed. A processor is coupled to a memory. A processor renders the geometry of a scene into a geometry buffer. For a given light source in the scene, the processor initiates two shader pipeline passes to determine which pixels in the geometry buffer to light. On the first pass, the processor renders a front-side of a light volume corresponding to the light source. Any pixels of the geometry buffer which are in front of the front-side of the light volume are marked as pixels to be discarded. Then, during the second pass, only those pixels which were not marked to be discarded are sent to the pixel shader. This approach helps to reduce the overhead involved in applying a lighting effect to the scene by reducing the amount of work performed by the pixel shader.