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公开(公告)号:US20160118009A1
公开(公告)日:2016-04-28
申请号:US14644692
申请日:2015-03-11
Applicant: AU Optronics Corporation
Inventor: Chih-Lung LIN , Yuan-Wei DU , Fu-Hsing CHEN , Chun-Da TU
IPC: G09G3/36 , H03K19/0185
CPC classification number: G09G3/3677 , G09G3/20 , G09G2310/0267 , G09G2310/0286 , G09G2310/0289 , H03K19/018507
Abstract: A display panel includes gate lines and a gate driver. The gate driver includes series coupled driving stages, in which an N-th driving stage of the series-coupled driving stages includes a driving unit and an input control unit. The driving unit transmits a first clock signal according to a control voltage level of a control node, so as to output a gate-driving signal. The input control unit transmits the gate-driving signal outputted from an (N−1)-th driving stage to the control nodes, so as to adjust the control voltage level to one of a first voltage level and a second voltage level. A predetermined time interval is present between a rising edge of the first clock signal and a falling edge of the second clock signal. During the predetermined time interval, the control voltage level is pulled to the first voltage level by the input control unit.
Abstract translation: 显示面板包括栅极线和栅极驱动器。 栅极驱动器包括串联耦合驱动级,其中串联耦合驱动级的第N驱动级包括驱动单元和输入控制单元。 驱动单元根据控制节点的控制电压电平发送第一时钟信号,以输出栅极驱动信号。 输入控制单元将从第(N-1)驱动级输出的栅极驱动信号发送到控制节点,以将控制电压电平调整为第一电压电平和第二电压电平之一。 在第一时钟信号的上升沿和第二时钟信号的下降沿之间存在预定的时间间隔。 在预定时间间隔期间,通过输入控制单元将控制电压电平拉至第一电压电平。
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公开(公告)号:US20200294436A1
公开(公告)日:2020-09-17
申请号:US16653459
申请日:2019-10-15
Applicant: AU Optronics Corporation
Inventor: Po-Cheng LAI , Mao-Hsun CHENG , Cheng-Han HUANG , Yung-Chih CHEN , Ching-Sheng CHENG , Chih-Lung LIN
Abstract: A shift register circuit and a gate driver including the shift register circuit. The shift register circuit includes an input circuit, a drive circuit, a pull-down circuit, a regulator circuit and a pull-up circuit. The input circuit is configured to receive a first clock signal and is coupled to the first node. The driving circuit is configured to receive the first clock signal and a second clock signal. The input circuit is coupled to the first node. The pull-down circuit is configured to receive the voltage of the first node. The pull-down circuit is coupled to the first node and an output terminal. The pull-down circuit outputs the first voltage to the output terminal in response to the voltage of the first node.
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公开(公告)号:US20170123556A1
公开(公告)日:2017-05-04
申请号:US15189468
申请日:2016-06-22
Applicant: AU Optronics Corporation
Inventor: Chih-Lung LIN , Po-Chun Lai , Chia-En Wu , Chien-Chuan Ko , Meng-Chieh Tsai
CPC classification number: G06F3/0416 , G06F3/0412 , G06F3/044 , G09G3/20 , G09G3/3677 , G09G3/3696 , G09G2300/0842 , G09G2310/0267 , G09G2310/0286 , G11C19/28
Abstract: A shift register circuit includes a driving unit outputting a first scan signal according to a first clock signal; a pull up unit outputting a driving voltage according to one of a second scan signal and a third scan signal; a pull down unit pulling down voltage of an output end according to a second clock signal; a pull down control unit controlling the voltage of the output end and a driving node according to the first clock signal; a reset unit pulling down the voltage level of the driving node according to a touch-enable signal; and an electric storage unit adjusting the voltage of the driving node according to a touch-stop signal. When the touch-enable signal is enabled, the clock signals and the touch-stop signal are disabled, and when the touch-stop signal is enabled, the clock signals and the touch-enable signal are disabled.
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公开(公告)号:US20200158567A1
公开(公告)日:2020-05-21
申请号:US16590961
申请日:2019-10-02
Applicant: AU Optronics Corporation , NATIONAL CHENG KUNG UNIVERSITY
Inventor: Chih-Lung LIN , Fu-Hsing CHEN , Chia-Lun LEE , Chia-En WU , Jian-Shen YU
Abstract: An optical sensing circuit includes a first light sensor, a second light sensor, a third light sensor, a capacitor, and a sampling circuit. The first light sensor, the second light sensor, and the third light sensor are respectively covered by a first color filter, a second color filter, and a third color filter. The first light sensor is coupled to the capacitor, the sampling circuit, and the third light sensor. The second light sensor is coupled to the first light sensor and is configured to receive a first sensing signal. The third light sensor is coupled between the first light sensor and a voltage source.
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公开(公告)号:US20190012977A1
公开(公告)日:2019-01-10
申请号:US15804154
申请日:2017-11-06
Applicant: AU Optronics Corporation , National Cheng Kung University
Inventor: Chih-Lung LIN , Po-Syun Chen , Cheng-Chiu Pai
IPC: G09G3/36 , G02F1/1345 , G02F1/1368 , G02F1/133
Abstract: An Liquid crystal display panel is provided. The Liquid crystal display panel includes a plurality of pixel elements arranged as a pixel array. The Liquid crystal display panel receives a plurality of data signals, a plurality of gate driving signals, a plurality of control signals, and an extra data signal. Each of the gate driving signals includes a gate pulse; each of the data signals includes a data voltage; the extra data signal includes a data voltage; and each of the control signals includes a gate pulse and a data voltage.
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公开(公告)号:US20170276541A1
公开(公告)日:2017-09-28
申请号:US15450583
申请日:2017-03-06
Applicant: AU Optronics Corporation
Inventor: Chih-Lung LIN , Chia-En WU , Po-Syun CHEN , Fu-Hsing CHEN , Ming-Xun WANG , Ching-En LEE , Po-Cheng LAI , Jian-Shen YU
CPC classification number: G01J1/0214 , G01J1/0488 , G01J1/46 , G01J2001/4473 , G06F3/0304 , G06F3/042
Abstract: An optical sensing circuit has a plurality of optical sensing units arranged so that the optical sensing circuit is ambient light insensitive or sensitive to light within certain spectrum. The sensitive spectra corresponding to the plurality of optical sensing units are different from one another.
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公开(公告)号:US20210125547A1
公开(公告)日:2021-04-29
申请号:US17075066
申请日:2020-10-20
Applicant: AU Optronics Corporation
Inventor: Chih-Lung LIN , Po-Cheng LAI , Ting-Ching CHU , Po-Chun LAI , Mao-Hsun CHENG
IPC: G09G3/32
Abstract: A pixel circuit including a compensation circuit, a writing circuit, a light emitting element, and a power supplying circuit is provided. The compensation circuit comprises a first node, and provides a driving current to the light emitting element according to a voltage of the first node and a system high voltage. The writing circuit provides a data voltage to the compensation circuit according to a first control signal so that the compensation circuit sets the voltage of the first node. The power supplying circuit selectively couples the compensation circuit to the light emitting element, and provides the system high voltage and a system low voltage to the compensation circuit, in which the system low voltage is configured to reset the voltage of the first node. The first control signal and the second control signal are opposite to the first emission signal and the second emission signal, respectively.
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