公开(公告)号：US20170276541A1

公开(公告)日：2017-09-28

申请号：US15450583

申请日：2017-03-06

Applicant: AU Optronics Corporation

Inventor： Chih-Lung LIN ,  Chia-En WU ,  Po-Syun CHEN ,  Fu-Hsing CHEN ,  Ming-Xun WANG ,  Ching-En LEE ,  Po-Cheng LAI ,  Jian-Shen YU

IPC: G01J1/02 ,  G01J1/04 ,  G01J1/46

CPC classification number: G01J1/0214 ,  G01J1/0488 ,  G01J1/46 ,  G01J2001/4473 ,  G06F3/0304 ,  G06F3/042

Abstract: An optical sensing circuit has a plurality of optical sensing units arranged so that the optical sensing circuit is ambient light insensitive or sensitive to light within certain spectrum. The sensitive spectra corresponding to the plurality of optical sensing units are different from one another.

公开(公告)号：US20210125547A1

公开(公告)日：2021-04-29

申请号：US17075066

申请日：2020-10-20

Applicant: AU Optronics Corporation

Inventor： Chih-Lung LIN ,  Po-Cheng LAI ,  Ting-Ching CHU ,  Po-Chun LAI ,  Mao-Hsun CHENG

IPC: G09G3/32

Abstract: A pixel circuit including a compensation circuit, a writing circuit, a light emitting element, and a power supplying circuit is provided. The compensation circuit comprises a first node, and provides a driving current to the light emitting element according to a voltage of the first node and a system high voltage. The writing circuit provides a data voltage to the compensation circuit according to a first control signal so that the compensation circuit sets the voltage of the first node. The power supplying circuit selectively couples the compensation circuit to the light emitting element, and provides the system high voltage and a system low voltage to the compensation circuit, in which the system low voltage is configured to reset the voltage of the first node. The first control signal and the second control signal are opposite to the first emission signal and the second emission signal, respectively.

公开(公告)号：US20200294436A1

公开(公告)日：2020-09-17

申请号：US16653459

申请日：2019-10-15

Applicant: AU Optronics Corporation

Inventor： Po-Cheng LAI ,  Mao-Hsun CHENG ,  Cheng-Han HUANG ,  Yung-Chih CHEN ,  Ching-Sheng CHENG ,  Chih-Lung LIN

IPC: G09G3/20 ,  G11C19/28

Abstract: A shift register circuit and a gate driver including the shift register circuit. The shift register circuit includes an input circuit, a drive circuit, a pull-down circuit, a regulator circuit and a pull-up circuit. The input circuit is configured to receive a first clock signal and is coupled to the first node. The driving circuit is configured to receive the first clock signal and a second clock signal. The input circuit is coupled to the first node. The pull-down circuit is configured to receive the voltage of the first node. The pull-down circuit is coupled to the first node and an output terminal. The pull-down circuit outputs the first voltage to the output terminal in response to the voltage of the first node.