公开(公告)号：US20250167192A1

公开(公告)日：2025-05-22

申请号：US18518184

申请日：2023-11-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Arsalan ALAM ,  Chandra Sekhar MANDALAPU ,  Liwei WANG ,  Omkar Deepak GUPTE ,  Anadi SRIVASTAVA ,  Sai VADLAMANI ,  Sri Ranga Sai BOYAPATI ,  Manish DUBEY

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: Disclosed herein is an integrated circuit die stack and an integrated circuit die package assembly having the integrated circuit die stack. The integrated circuit die stack includes first plurality of integrated circuit dice disposed in a first tier of the die stack, and the first plurality of integrated circuit dice include a first integrated circuit die and a bridge die. The integrated circuit die stack further includes a second plurality of integrated circuit dice disposed in a second tier of the die stack, and the second plurality of integrated circuit dice are stacked vertically above the first plurality of the integrated circuit dice of the first tier and include a second integrated circuit die and a third integrated circuit die. The bridge die couples with both the second integrated circuit die and the third integrated circuit die.

公开(公告)号：US20240404897A1

公开(公告)日：2024-12-05

申请号：US18676665

申请日：2024-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant KULKARNI ,  Raja SWAMINATHAN ,  Mihir PANDYA ,  Liwei WANG ,  Samuel NAFFZIGER

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18

Abstract: A chip complex is provided that includes at least a first IC die present in a first common tier, a passive interposer, and a plurality of IC dies present in a second common tier. The passive interposer includes an interconnect formed in a back end of the line (BEOL) region. The first IC die present in the first common tier are hybrid bonded to a top side of the passive interposer. The plurality of IC dies present in the second common tier are also hybrid bonded to a bottom side of the passive interposer.