公开(公告)号：US20180261573A1

公开(公告)日：2018-09-13

申请号：US15454520

申请日：2017-03-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  I-Cheng WANG ,  Wun-Jheng SYU

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/29 ,  H01L23/24 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/24 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06586

Abstract: A semiconductor device package includes a first circuit layer, at least one electrical element, a first molding layer, an electronic component and a second molding layer. The at least one electrical element is disposed over a first surface of the first circuit layer and electrically connected to the first circuit layer. The first molding layer is disposed over the first surface of the first circuit layer. The first molding layer encapsulates an edge of the at least one electrical element, and a lower surface of the first molding layer and a lower surface of the at least one electrical element are substantially coplanar. The electronic component is disposed over a second surface of the first circuit layer and is electrically connected to the first circuit layer. The second molding layer is disposed over the second surface of the first circuit layer and encapsulates the electronic component.

公开(公告)号：US20200080841A1

公开(公告)日：2020-03-12

申请号：US16683117

申请日：2019-11-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Chung CHEN ,  Hsun-Wei CHAN ,  Lu-Ming LAI ,  Kuang-Hsiung CHEN

IPC: G01C3/08

Abstract: An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.

公开(公告)号：US20180350626A1

公开(公告)日：2018-12-06

申请号：US16102527

申请日：2018-08-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  Yu-Ying LEE ,  Yu-Tzu PENG

IPC: H01L21/48 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.

公开(公告)号：US20240102799A1

公开(公告)日：2024-03-28

申请号：US18530130

申请日：2023-12-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Chung CHEN ,  Hsun-Wei CHAN ,  Lu-Ming LAI ,  Kuang-Hsiung CHEN

IPC: G01C3/08

CPC classification number: G01C3/08

Abstract: An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.

公开(公告)号：US20190198469A1

公开(公告)日：2019-06-27

申请号：US16293606

申请日：2019-03-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Kuang-Hsiung CHEN ,  Yu-Hsuan TSAI ,  Yu-Ying LEE ,  Sheng-Ming WANG ,  Wun-Jheng SYU

IPC: H01L23/00 ,  B81C1/00 ,  H01L25/00 ,  H01L25/065 ,  B81B7/00 ,  H01L21/56 ,  H01L23/31

Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.

公开(公告)号：US20180145037A1

公开(公告)日：2018-05-24

申请号：US15873784

申请日：2018-01-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Sheng-Ming WANG ,  Kuang-Hsiung CHEN ,  Yu-Ying LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units which comprise a substrate unit; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures which comprise a semiconductor package structure comprising the substrate unit, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.

公开(公告)号：US20160240462A1

公开(公告)日：2016-08-18

申请号：US14624388

申请日：2015-02-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  Yu-Ying LEE ,  Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.

Abstract translation: 本公开涉及一种半导体衬底结构，半导体封装及其制造方法。 半导体衬底结构包括导电结构，电介质结构和金属凸块。 导电结构具有第一导电表面和第二导电表面。 电介质结构具有第一电介质表面和第二电介质表面。 第一导电表面不从第一电介质表面突出。 第二导电表面从第二电介质表面凹陷。 金属凸块设置在电介质结构的电介质开口中，并且物理地和电连接到第二导电表面。 金属凸块具有凹面。

公开(公告)号：US20140327125A1

公开(公告)日：2014-11-06

申请号：US14268981

申请日：2014-05-02

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu CHEN ,  Sheng-Ming WANG ,  Kuang-Hsiung CHEN ,  Yu-Ying LEE

IPC: H01L23/00 ,  H01L21/50

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.

Abstract translation: 提供半导体封装结构及其制造方法。 所述制造方法包括：提供衬底条，所述衬底条包括多个衬底单元; 在所述多个基板单元上设置多个芯片; 将包装密封剂设置在所述衬底条上以封装所述芯片; 在所述包装密封剂的顶表面上形成耐翘曲层; 并且分割所述衬底条以分离所述多个衬底单元以进一步制造多个半导体封装结构，其中所述耐翘曲层由具有选定厚度的选定材料形成以使所述半导体封装结构的翘曲变化在 温度在25℃至260℃之间，以小于560微米。

公开(公告)号：US20220187068A1

公开(公告)日：2022-06-16

申请号：US17684374

申请日：2022-03-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Chung CHEN ,  Hsun-Wei CHAN ,  Lu-Ming LAI ,  Kuang-Hsiung CHEN

IPC: G01C3/08

Abstract: An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.

公开(公告)号：US20190088626A1

公开(公告)日：2019-03-21

申请号：US16194265

申请日：2018-11-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  I-Cheng WANG ,  Wun-Jheng SYU

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/24 ,  H01L23/29 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00

Abstract: A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.